KR950007208Y1 - Lead frame - Google Patents
Lead frame Download PDFInfo
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- KR950007208Y1 KR950007208Y1 KR92015769U KR920015769U KR950007208Y1 KR 950007208 Y1 KR950007208 Y1 KR 950007208Y1 KR 92015769 U KR92015769 U KR 92015769U KR 920015769 U KR920015769 U KR 920015769U KR 950007208 Y1 KR950007208 Y1 KR 950007208Y1
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- KR
- South Korea
- Prior art keywords
- resin
- lead frame
- paddle
- flow path
- package
- Prior art date
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
내용 없음.No content.
Description
제1a도, 제1b도는 종래 반도체 패키비용 리드프레임의 저면도 및 a도에 도시한 리드프레임을 이용하여 제작한 반도체 패키지의 종단면도.1A and 1B are bottom views of conventional semiconductor package cost leadframes and longitudinal cross-sectional views of semiconductor packages fabricated using the leadframes shown in FIG.
제2a도, 제2b도는 본 고안에 의한 반도체 패키지용 리드플레임의 저면도 및 a도에 도시한 리드프레임을 이용하여 제작한 반도체 패키지의 종단면도.FIG. 2A and FIG. 2B are longitudinal cross-sectional views of a semiconductor package manufactured by using the lead frame shown in FIG.
제3a도, 제3b도, 제3c도, 제3d도는 본 고안 리드프레임의 패들에 형성된 레진유로의 여러 실시례를 보인 저면도.3a, 3b, 3c, 3d is a bottom view showing various embodiments of the resin flow path formed in the paddle of the present invention lead frame.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 패들 3 : 인너리드1: Paddle 3: Inner Lead
10 : 레진(Resin)유로10: Resin Euro
본 고안은 반도체 패키지 제조에 사용되는 리드프레임(lead frmae)의 패들(paddle)구조에 관한 것으로, 특히 패들의 하면에 몰드공정시 레진(resing)의 흐름을 보다 원활하게 하기 위한 레진유로를 형성하여 레진의 충진 효율을 높임으로써 박형(薄形) 패키지(thin package)에서의 레진 미충진 불량 및 관통 보이드(void)발생을 최소화 하도록 한 반도체 패키지용 리드프레임에 관한 것이다.The present invention relates to a paddle structure of the lead frame (lead frmae) used in the manufacture of a semiconductor package, in particular by forming a resin flow path on the lower surface of the paddle to facilitate the flow of the resin (resing) during the mold process The present invention relates to a lead frame for a semiconductor package that minimizes resin unfilled defects and through voids in a thin package by increasing the filling efficiency of the resin.
일반적으로 반도체 패키지의 제조에 사용되는 리드프레임은, 제1도에 도시한 바와같이, 양 사이드레일(side rail : 도시되지 않음)의 내측에 반도체칩이 부착되는 패들(1)이 타이바(tie bar)(2)(2')에 의하여 지지되어 있고, 상기 패들(1)의 양측에는 반도체 칩에 와이어 본딩(wite bonding)되는 다수개의 인러리드(3)가 배열된 구조로 되어 있으며, 상기 인너리드(3)는 댐바(dambar : 도시되지 않음)에 의하여 지지되어 있다.In general, the lead frame used in the manufacture of a semiconductor package, as shown in Figure 1, the paddle (1) to which the semiconductor chip is attached to the inside of both side rails (not shown) tie and a plurality of inlets (3) which are wire bonded to a semiconductor chip on both sides of the paddle (1), and are supported by two bars (2) and 2 '. The lid 3 is supported by a dambar (not shown).
이와 같이 된 리드프레임의 패들(1)에는 제2도에 도시한 바와 같이, 반도체 칩(4)과 탑재되어 금속와이어(5)에 의해 인러리드(3)와 전기적으로 접속 연결되고, 와이어 본딩된 반도체 칩(4)과 리드프레임의 인너리드(3)를 포함하는 일정면적을 레진(에폭시수지)(6)으로 밀봉시키는 것에 의하여 소정형태의 반도체 패키지를 제조하게 되는 것이다.As shown in FIG. 2, the lead frame paddle 1 of the lead frame is mounted with the semiconductor chip 4, electrically connected to the inlead 3 by the metal wire 5, and wire-bonded. By sealing a predetermined area including the semiconductor chip 4 and the inner lead 3 of the lead frame with the resin (epoxy resin) 6, a semiconductor package of a predetermined type is manufactured.
여기서 와이어 본딩된 반도체 칩(4)과 리드프레임의 인너리드(3)를 포함하는 일정면적을 레진(6)으로 밀봉시켜 패키지 몸체를 형성하는 작업을 몰딩(molding)공정이라 하고 있는데, 이는 일반적으로 트랜스퍼 몰딩금형을 이용하여 행하고 있다.In this case, a process of forming a package body by sealing a predetermined area including the wire bonded semiconductor chip 4 and the inner lead 3 of the lead frame with the resin 6 is called a molding process. This is done using a transfer molding mold.
그러나, 상기한 바와 같은 종래의 패들(1) 구조를 갖는 리드프레임을 이용하여 반도체 패키지를 제조함에 있어서는, 일반적인 패키지를 제조함에 있어서는 그렇지 않으나, 박형 패키지(thin package) 예컨대, 패키지 몸체의 두께가 얇은 박형 스몰 아웃라인 패키지(TSOP) 및 박형 퀴드 플랫 패키지(TQFP)등을 제조함에 있어서는, 몰딩공정시 리드프레임의 패들(1)과 성형되는 패키지 몸체 하면과의 공간이 협소하여 충진되는 레진(6)의 흐름이 원활하지 않음으로써 미충진등과 같은 성형 불량이 다발하게 되고, 관통 보이드의 원인이 되는 문제가 있었다.However, in manufacturing a semiconductor package using a lead frame having a conventional paddle 1 structure as described above, in manufacturing a general package, this is not the case, but a thin package such as a thin package body In manufacturing the thin small outline package (TSOP) and the thin quick flat package (TQFP), the resin 6 filled with a narrow space between the paddle 1 of the lead frame and the bottom surface of the package body to be molded during the molding process. Due to the incomplete flow of the mold, molding defects such as unfilled and the like occur frequently, and there is a problem that causes through voids.
이를 감안하여 안출한 본 고안의 목적은 리드프레임의 패들을 몰딩공정시 레진의 흐름을 원활하도록 개조하여 레진의 미충진불량 및 관통 보이드 발생을 억제하도록 한 반도체 패키지용 리드프레임을 제공함에 있다.In view of this, an object of the present invention is to provide a lead frame for a semiconductor package, in which a paddle of a lead frame is modified to smooth resin flow during molding process, thereby preventing unfilled defects and through voids in the resin.
상기와 같은 본 고안의 목적을 달성하기 위하여, 반도체칩이 탑재되는 패들의 양측에 다수개의 인너리드가 배열되고, 상기 패들의 하면에 몰드공정시 레진의 흐름을 보다 원활하게 하기 위한 레진유로가 형성된 반도체 패키지용 리드프레임에 있어서, 상기 레진유로는 그 두께 및 면적을 패들 두께 및 면적의 50~90%이내로 형성하고, 몰드레진의 흐름경로를 고려하여 게이트방향과 일치되도록 형성하되, 그 입구 및 출구가 대각선의 방향으로 각진 형태로 형성하여서 됨을 특징으로 하는 반도체 패키지용 리드프레임가 제공된다.In order to achieve the object of the present invention as described above, a plurality of inner leads are arranged on both sides of the paddle on which the semiconductor chip is mounted, and a resin flow path is formed on the lower surface of the paddle to smooth the flow of the resin during the mold process. In the lead frame for a semiconductor package, the resin flow channel is formed within 50 ~ 90% of the thickness and area of the paddle thickness, and formed to match the gate direction in consideration of the flow path of the mold resin, the inlet and outlet There is provided a lead frame for a semiconductor package, characterized in that is formed in an angled shape in the diagonal direction.
상기와 같이 된 본 고안의 리드프레임에 의하면 씬패키지의 몰딩공정시, 레진충진 효율이 보다 높아지므로 박형 패키지에서의 미충진 불량 및 관통보이드의 발생을 최소화할 수 있다는 효과가 있고, 패키지 하부의 두께가 두꺼워지므로 몰드밸런스(Balance)를 맞추는데 매우 효과적이다.According to the lead frame of the present invention as described above, since the resin filling efficiency is higher during the molding process of the thin package, it is effective to minimize the occurrence of unfilled defects and through-voids in the thin package, and the thickness of the lower part of the package It becomes thicker, which is very effective for balancing the balance.
또한, 리드프레임의 패들과 레진과의 접착력을 향상시킬 수 있다는 효과도 있다.In addition, there is an effect that can improve the adhesion between the paddle and the resin of the lead frame.
이하, 상기한 바와 같은 본 고안에 의한 반도체 패키지용 리드프레임을 첨부도면에 의거하여 보다 상세히 설명한다.Hereinafter, the lead frame for a semiconductor package according to the present invention as described above will be described in more detail based on the accompanying drawings.
제2도의 (a)(b)는 본 고안에 의한 리드프레미의 저면도 및 (a)에 도시한 리드프레임을 이용하여 제작한 반도체 패키지의 종단면도이고, 제3도의 (a)(b)(c)(d)는 본 고안의 패들에 형성되는 레진유로의 여러 실시례를 보인 저면도로서, 이에 도시한 바와 같이, 본 고안에 의한 반도체 패키지용 리드프레임은, 일반적인 리드 프레임의 패들(1) 하면에 몰드공정시 레진의 흐름을 보다 원활하게 하기위한 레진유로(10)를 형성하여 레진의 충진효율을 높임으로써 미충진 및 관통보이드 발생을 억제할 수 있도록 구성함을 특징으로 하고 있다.(A) and (b) of FIG. 2 are longitudinal cross-sectional views of a semiconductor package fabricated using the bottom view of the lead premises according to the present invention and the lead frame shown in (a), and (a) and (b) of FIG. c) (d) is a bottom view showing various embodiments of the resin flow path formed in the paddle of the present invention, as shown in the lead frame for a semiconductor package according to the present invention, the paddle (1) of the general lead frame Resin flow path 10 is formed on the lower surface to smooth the flow of the resin during the mold process to increase the filling efficiency of the resin is characterized in that it is configured to suppress the unfilled and through-void generation.
상기 레진유로(10)는 에칭(Etching) 및 스탬핑(Stamping)에 의해 형성되는 바, 두께는 패들(1) 두께의 90%를 넘지 않도록 하고, 면적은 패들(1) 전체 면적의 90%를 넘지 않도록 함이 바람직하다. 그 하한치는 50%로 하는 것이 바람직하다.The resin flow path 10 is formed by etching and stamping, the thickness of which does not exceed 90% of the thickness of the paddle 1, and the area does not exceed 90% of the total area of the paddle 1. It is preferable to avoid. It is preferable to make the lower limit into 50%.
또한, 상기 레진유로(10)를 형성함에 있어서는 몰드레진의 흐름경로를 고려하여 게이트 방향과 일치되게 함이 바람직하며, 형상은 제3도에 도시한 바와 같이, 각진 형태, 또는 곡선형태등 여러형상으로 형성할 수 있는 바, 특히 제3도의 (a) 도시한 바와 같이, 입구 및 출구가 대각선의 방향으로 각진 형태로 형성하는 것이 바람직하다.In addition, in forming the resin flow path 10, it is preferable to match the gate direction in consideration of the flow path of the mold resin, and the shape is various shapes such as an angular shape or a curved shape as shown in FIG. In particular, as shown in (a) of FIG. 3, the inlet and the outlet are preferably formed in an angled shape in a diagonal direction.
도면에서 종래 구성과 동일한 부분에 대해서는 동일부호를 부여하였다.In the drawings, the same reference numerals are given to the same parts as in the prior art.
이와같이 구성된 리드프레임을 이용하여 제작한 반도체 패키지가 제2도의 (b)에 도시되어 있는 바, 본 고안의 레진유로(10)에 의해 레진(6)이 미충진 및 관통보이드 없이 충진되어 패키지 몸체를 형성하고 있으며, 패키지 몸체의 하부가 종래에 비해 레진유로의 높이만큼 두꺼워지므로 몰두레진의 밸런스가 맞추어지고, 리드프레임의 패들과 몰드레진의 접착력이 향상됨을 알 수 있다.The semiconductor package fabricated using the lead frame configured as described above is illustrated in FIG. 2 (b), and the resin 6 is filled with no filling and through-voids by the resin flow path 10 of the present invention, thereby providing a package body. Since the lower part of the package body is thicker as the height of the resin flow path as compared with the related art, the balance of the molybdenum resin is balanced and the adhesion between the paddle and the mold resin of the lead frame is improved.
이상에서 상세히 살펴본 바와 같이 본 고안에 의한 반도체 패키지용 리드프레임은 반도체칩이 탑재되는 패들의 하면에 몰드공정시 레진의 흐름을 원활하게 하기위한 소정형태의 레진유로를 형성하여 레진의 충진효율을 가일층 높일 수 있도록 구성한 것으로, 이와같이된 본 고안의 리드프레임을 이용하게 되면 종래의 박형 패키지 제조시 다발하였던 미충진 불량 및 관통보이드 발생을 최소화하는 효과가 있고, 패키지 하부의 두께가 두꺼워지므로 몰드밸런스를 맞추는데 매우 효과적이며, 또한 리드프레임의 패들과 몰드레진간의 접착력이 증대되는 효과도 있다.As described in detail above, the lead frame for a semiconductor package according to the present invention forms a resin flow path of a predetermined type to smooth the flow of resin during a mold process on the lower surface of a paddle on which a semiconductor chip is mounted, thereby further improving the filling efficiency of the resin. The lead frame of the present invention has the effect of minimizing the occurrence of unfilled defects and through-voids, which have been frequently caused in the manufacture of the conventional thin package, and the thickness of the lower part of the package becomes thicker to adjust the mold balance. It is very effective and also has the effect of increasing the adhesion between the paddle and the mold resin of the lead frame.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR92015769U KR950007208Y1 (en) | 1992-08-21 | 1992-08-21 | Lead frame |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR92015769U KR950007208Y1 (en) | 1992-08-21 | 1992-08-21 | Lead frame |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR940006489U KR940006489U (en) | 1994-03-25 |
| KR950007208Y1 true KR950007208Y1 (en) | 1995-09-02 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR92015769U KR950007208Y1 (en) | 1992-08-21 | 1992-08-21 | Lead frame |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR950007208Y1 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100640556B1 (en) * | 2006-03-09 | 2006-11-01 | 주식회사 티에스피 | Semiconductor device |
-
1992
- 1992-08-21 KR KR92015769U patent/KR950007208Y1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR940006489U (en) | 1994-03-25 |
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