JPS6233748B2 - - Google Patents
Info
- Publication number
- JPS6233748B2 JPS6233748B2 JP58089103A JP8910383A JPS6233748B2 JP S6233748 B2 JPS6233748 B2 JP S6233748B2 JP 58089103 A JP58089103 A JP 58089103A JP 8910383 A JP8910383 A JP 8910383A JP S6233748 B2 JPS6233748 B2 JP S6233748B2
- Authority
- JP
- Japan
- Prior art keywords
- mold
- resin
- lead frame
- space
- frame
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000011347 resin Substances 0.000 claims description 31
- 229920005989 resin Polymers 0.000 claims description 31
- 238000002347 injection Methods 0.000 claims description 18
- 239000007924 injection Substances 0.000 claims description 18
- 239000004065 semiconductor Substances 0.000 description 15
- 238000007789 sealing Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000000465 moulding Methods 0.000 description 3
- 239000011148 porous material Substances 0.000 description 3
- 230000008595 infiltration Effects 0.000 description 1
- 238000001764 infiltration Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000001721 transfer moulding Methods 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Description
【発明の詳細な説明】
本発明は半導体装置の封止において用いるリー
ドフレームに関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a lead frame used in encapsulating a semiconductor device.
周知のように、半導体装置、半導体集積回路装
置の製造において、半導体素子、ワイヤ、リード
内端部等の主要部をレジンでモールドする工程が
ある。 As is well known, in the manufacture of semiconductor devices and semiconductor integrated circuit devices, there is a step of molding main parts such as semiconductor elements, wires, and inner ends of leads with resin.
ところで、このモールドをトランスフアモール
ドで行なう際、第１図で示すように、レジンはリ
ードフレーム１を挾持するモールド上型２および
モールド下型３からなるモールド空間４内に向か
つてモールド下型３の上部に設けられた注入口
（ゲート）５から勢いよく流入する。しかし、注
入口５は一般にモールド上型２またはモールド下
型３の表面部分に設けられる。したがつて、注入
口５はリードフレーム１の一面に位置することに
なり、流入するレジンは注入口５に最も近いリー
ド６に対して斜方向に衝突する。この結果、リー
ド６の一面（図では上面）側に流れのかげがで
き、レジンモールド後この位置に気胞（ボイド）
７が発生する。この気胞７は水分の浸入の原因と
もなり半導体装置の耐湿性の低下を来し好ましく
ない。 By the way, when performing this molding by transfer molding, as shown in FIG. It flows in forcefully from the injection port (gate) 5 provided at the top of the cell. However, the injection port 5 is generally provided on a surface portion of the upper mold 2 or the lower mold 3. Therefore, the injection port 5 is located on one side of the lead frame 1, and the inflowing resin obliquely collides with the lead 6 closest to the injection port 5. As a result, a shadow of the flow is created on one side of the lead 6 (the top side in the figure), and air pores (voids) are formed at this position after resin molding.
7 occurs. This air pore 7 is also a cause of moisture infiltration, resulting in a decrease in the moisture resistance of the semiconductor device, which is undesirable.
したがつて、本発明の目的は耐湿性の優れた半
導体装置を形成できるようにしたリードフレーム
を提供することにある。 SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a lead frame with which a semiconductor device with excellent moisture resistance can be formed.
以下実施例により本発明を詳細に説明する。 The present invention will be explained in detail below with reference to Examples.
第２図は本発明の半導体装置の封止に用いるリ
ードフレーム８とモールド型９との関係を示す。
このリードフレーム８は２本の平行な外枠１０
と、この外枠１０に直交しかつ両端をそれぞれの
外枠１０に繋がる平行な２本の内枠１１と、一方
の内枠１１から延び内枠１１と外枠１０とからな
る枠の中心に位置する矩形のタブ１２を支持する
屈曲したタブリード１３と、このタブ１２に向か
つてそれぞれ両側の内枠１１から延びる複数のリ
ード１４と、それぞれのリード１４および外枠１
０とを直線的に繋ぐタイバー１５とからなつてい
る。また、このリードフレーム８の一方の外枠１
０の内周縁であつて、タイバー１５とタイバー１
５との間の部分にはレジン注入空間１６となるよ
うに切欠部が外枠１０の外周縁近くまで形成され
ている。 FIG. 2 shows the relationship between a lead frame 8 and a mold 9 used for sealing the semiconductor device of the present invention.
This lead frame 8 consists of two parallel outer frames 10.
and two parallel inner frames 11 that are perpendicular to this outer frame 10 and have both ends connected to the respective outer frames 10, and a frame that extends from one inner frame 11 and is made up of the inner frame 11 and the outer frame 10. A bent tab lead 13 supporting the rectangular tab 12 located therein, a plurality of leads 14 extending from the inner frame 11 on both sides towards the tab 12, and the respective leads 14 and the outer frame 1.
0 and a tie bar 15 that linearly connects. Also, one outer frame 1 of this lead frame 8
0, and tie bar 15 and tie bar 1
5, a notch is formed close to the outer peripheral edge of the outer frame 10 to form a resin injection space 16.
このような形状のリードフレーム８のタブ１２
上に半導体素子１７を取り付けるとともに、この
半導体素子１７の電極とリード１４の内端とをワ
イヤ１８で接続する。つぎに、このリードフレー
ム８を第２図に鎖線で示すようなモールド型９に
装着する。このとき、第３図で示すように、リー
ドフレーム８はモールド型９の上型１９と下型２
０との間に挾持される。そして、上型１９と下型
２０とによつて形成されるモールド空間２１は第
２図で示すように、平行な２本の外枠１０および
平行な２列のタイバー１５とからなる矩形枠より
もわずかに小さく形成されるようになつている。 Tab 12 of lead frame 8 shaped like this
A semiconductor element 17 is attached thereon, and the electrodes of this semiconductor element 17 and the inner ends of the leads 14 are connected with wires 18. Next, this lead frame 8 is mounted in a mold 9 as shown by the chain line in FIG. At this time, as shown in FIG.
It is held between 0 and 0. As shown in FIG. 2, the mold space 21 formed by the upper mold 19 and the lower mold 20 is formed by a rectangular frame consisting of two parallel outer frames 10 and two parallel rows of tie bars 15. It is also becoming slightly smaller.
一方、前記下型２０の中央上面には溶融状態の
レジンが流れるランナー溝２２が設けられてい
る。そして、このランナー溝２２はリードフレー
ム８のレジン注入空間１６の設けられた外枠１０
の外縁部と重なるようになつている。この結果、
ランナー溝２２とリードフレーム８のレジン注入
空間１６とは連通するようになる。また、第３図
で示すように、外枠１０のレジン注入空間１６の
両側壁と上型１９の下面および下型の上面とによ
つてレジン注入口（ゲート）２３が形成される。
ところで、このゲート２３はリードフレーム８の
板を部分的に切欠いて形成され、その流出方向は
リード１４の側面に当たるようになつている。ま
た、上型１９の下面には溝が設けられ、下型２０
と合せられるとモールド空間２１内の空気抜孔２
４を形作るようになつている。また、下型２０に
は上下動するノツクアウトピン２５が配置され、
上昇してモールド空間２１内からモールド製品を
押し出すようになつている。 On the other hand, a runner groove 22 through which molten resin flows is provided on the upper center surface of the lower mold 20. The runner groove 22 is connected to the outer frame 10 of the lead frame 8 in which the resin injection space 16 is provided.
It overlaps with the outer edge of. As a result,
The runner groove 22 and the resin injection space 16 of the lead frame 8 come to communicate with each other. Further, as shown in FIG. 3, a resin injection port (gate) 23 is formed by both side walls of the resin injection space 16 of the outer frame 10, the lower surface of the upper mold 19, and the upper surface of the lower mold.
Incidentally, this gate 23 is formed by partially cutting out a plate of the lead frame 8, and its outflow direction is made to hit the side surface of the lead 14. Further, a groove is provided on the lower surface of the upper mold 19, and the lower mold 20
When combined with the air vent hole 2 in the mold space 21
It is starting to form a 4. Further, a knockout pin 25 that moves up and down is arranged on the lower mold 20,
It is designed to rise and push out the molded product from inside the mold space 21.
つぎに、本発明のリードフレームを用いて半導
体装置を封止する方法について説明する。まず、
第２図および第３図で示すようにペレツトボンデ
イングおよびワイヤボンデイングされたリードフ
レーム８をモールド型９に取り付ける。その後、
ランナー溝２２に溶融したレジン２６を圧入する
と、レジン注入口２３を通つてモールド空間２１
内にレジン２６が勢いよく流入する。この際、前
記ゲート２３から流入するレジン２６は第３図の
矢印２７，２８で示すように、リード１４の上面
および下面に接触しながら流れる。また、リード
１４の板厚は0.25mmと薄いことから、流れのかげ
となるところ、すなわち渦を巻くところもない。
このため、従来のようにモールドされたレジン内
に気胞が発生することはほとんどなくなる。 Next, a method for sealing a semiconductor device using the lead frame of the present invention will be described. first,
As shown in FIGS. 2 and 3, a pellet-bonded and wire-bonded lead frame 8 is attached to a mold 9. As shown in FIGS. after that,
When the molten resin 26 is press-fitted into the runner groove 22, it passes through the resin injection port 23 and enters the mold space 21.
The resin 26 flows into the inside with force. At this time, the resin 26 flowing from the gate 23 flows while contacting the upper and lower surfaces of the lead 14, as shown by arrows 27 and 28 in FIG. In addition, since the lead 14 has a thin plate thickness of 0.25 mm, there is no shadow of the flow, that is, there is no swirl.
For this reason, air pores are almost never generated in the molded resin as in the past.
また、レジン２６がモールド空間２１内を突き
進むにしたがつて、モールド空間２１内の空気は
反対側の空気抜孔２４から抜けでる。この場合、
レジンはリードフレームの側面から注入されてい
るため、リード１４の上側にレジンが注入されて
いくスピードと、その下側にレジンが注入されて
いくスピードとをほぼ等しくできる。したがつて
上記上側に注入されるレジンと上記下側に注入さ
れるレジンとがほぼ同時に空気抜孔２４に達する
ことになる。したがつてモールド空間２１内部に
空気が残つている状態で上記空気抜孔２４がレジ
ンによつてふさがれてしまうことがない。したが
つて、空気抜を十分行うことができる。このた
め、ボイドのないモールド部を形成することがで
きる。 Furthermore, as the resin 26 advances through the mold space 21, the air within the mold space 21 escapes from the air vent hole 24 on the opposite side. in this case,
Since the resin is injected from the side surface of the lead frame, the speed at which the resin is injected into the upper side of the lead 14 and the speed at which the resin is injected into the lower side thereof can be approximately equal. Therefore, the resin injected into the upper side and the resin injected into the lower side reach the air vent hole 24 almost simultaneously. Therefore, the air vent hole 24 will not be blocked by the resin while air remains inside the mold space 21. Therefore, air can be removed sufficiently. Therefore, a void-free mold part can be formed.
その後、レジン２６が凝固した後、上型１９を
取り外すとともにノツクアウトピン２５を上昇さ
せて、モールド製品を取り出す。 Thereafter, after the resin 26 has solidified, the upper mold 19 is removed and the knockout pin 25 is raised to take out the molded product.
このような実施例によれば、モールド内部に気
胞が生じないので、耐湿性の優れた半導体装置を
得ることができる。 According to such an embodiment, since air bubbles are not generated inside the mold, a semiconductor device with excellent moisture resistance can be obtained.
また、この実施例ではモールド型のランナー溝
から支流を設け、それぞれのモールド空間に連通
するようにしなくとも、単にランナー溝の一部と
リードフレーム８のレンジ注入空間１６が部分的
に重なり合うようにすればよい。したがつて、モ
ールド型の単純化、統一化が図れることから製造
価格が安価となる実益がある。 Further, in this embodiment, a tributary flow is provided from the runner groove of the mold mold, and without communicating with each mold space, a part of the runner groove and the range injection space 16 of the lead frame 8 are simply overlapped. do it. Therefore, since the mold type can be simplified and unified, there is a practical benefit of lowering the manufacturing price.
また、リードフレームの外枠に設けたレジン注
入空間１６がゲートの一部を分担しかつそれは常
に新しいのを使うこととなるから、摩耗によつて
ゲートの大きさが大きく変化することはない。 Further, since the resin injection space 16 provided in the outer frame of the lead frame takes up part of the gate, and a new one is always used, the size of the gate does not change significantly due to wear.
さらに、リードフレームのレジン注入空間の幅
を選択形成することによつて、所望の注入条件を
得ることができる。例えば、レジン注入空間１６
の幅を内枠１１まで広げることもできる。したが
つて、モールド型の統一化汎用性の増大を図るこ
とができる。 Furthermore, desired injection conditions can be obtained by selectively forming the width of the resin injection space of the lead frame. For example, resin injection space 16
It is also possible to widen the width to the inner frame 11. Therefore, it is possible to unify the mold type and increase its versatility.
なお、本発明は前記実施例に限定されない。 Note that the present invention is not limited to the above embodiments.
以上のように、本発明のリードフレームによれ
ば封止時、モールド内部に気胞が発生することを
防止できるので、耐湿性の優れた半導体装置を得
ることができる。 As described above, according to the lead frame of the present invention, it is possible to prevent air bubbles from being generated inside the mold during sealing, so that a semiconductor device with excellent moisture resistance can be obtained.
また、本発明によれば、モールド型を安価に製
造することができるとともに、汎用性を増大する
ことができるなどの効果を奏する。 Further, according to the present invention, it is possible to manufacture a mold at a low cost, and the versatility can be increased.
第１図は従来の半導体装置の封止状態を示す一
部断面図、第２図は半導体装置の封止に用いる本
発明に係るリードフレームとモールド型との関係
を示す一部平面図、第３図は第２図―線に沿
う断面図である。
１…リードフレーム、２…モールド上型、３…
モールド下型、４…モールド空間、５…注入口
（ゲート）、６…リード、７…気胞（ボイド）、８
…リードフレーム、９…モールド型、１０…外
枠、１１…内枠、１２…タブ、１３…タブリー
ド、１４…リード、１５…ダイバー、１６…レジ
ン注入空間、１７…半導体素子、１８…ワイヤ、
１９…上型、２０…下型、２１…モールド空間、
２２…ランナー溝、２３…レジン注入口（ゲー
ト）、２４…空気抜孔、２５…ノツクアウトピ
ン、２６…レジン、２７，２８…矢印。
FIG. 1 is a partial cross-sectional view showing the sealed state of a conventional semiconductor device, and FIG. 2 is a partial plan view showing the relationship between a lead frame and a mold according to the present invention used for sealing the semiconductor device. FIG. 3 is a sectional view taken along the line in FIG. 2. 1...Lead frame, 2...Mold upper die, 3...
Mold lower mold, 4...Mold space, 5...Inlet (gate), 6...Lead, 7...Void, 8
...Lead frame, 9...Mold mold, 10...Outer frame, 11...Inner frame, 12...Tab, 13...Tab lead, 14...Lead, 15...Diver, 16...Resin injection space, 17...Semiconductor element, 18...Wire,
19... Upper mold, 20... Lower mold, 21... Mold space,
22...Runner groove, 23...Resin injection port (gate), 24...Air vent hole, 25...Knockout pin, 26...Resin, 27, 28...Arrow.
Claims (1)
るモールド上型とモールド下型に挾持されるリー
ドフレームにおいて、前記レジンの流通空間部と
前記モールド空間を連通させるようにリードフレ
ームの外枠の内縁側にレジン注入用切込空間部を
形成してなることを特徴とするリードフレーム。1. In a lead frame that is held between an upper mold and a lower mold that form a resin circulation space and a mold space, the inner edge side of the outer frame of the lead frame is arranged so that the resin circulation space and the mold space communicate with each other. A lead frame characterized in that a cut space for resin injection is formed in the lead frame.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58089103A JPS5910251A (en) | 1983-05-23 | 1983-05-23 | Lead frame |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58089103A JPS5910251A (en) | 1983-05-23 | 1983-05-23 | Lead frame |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9028675A Division JPS59969B2 (en) | 1975-07-25 | 1975-07-25 | Method for sealing semiconductor devices |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5910251A JPS5910251A (en) | 1984-01-19 |
| JPS6233748B2 true JPS6233748B2 (en) | 1987-07-22 |
Family
ID=13961547
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58089103A Granted JPS5910251A (en) | 1983-05-23 | 1983-05-23 | Lead frame |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5910251A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02135765A (en) * | 1988-11-16 | 1990-05-24 | Matsushita Electron Corp | Lead frame for semiconductor device |
| US5275546A (en) * | 1991-12-30 | 1994-01-04 | Fierkens Richard H J | Plastic encapsulation apparatus for an integrated circuit lead frame and method therefor |
| JP6539942B2 (en) * | 2014-01-09 | 2019-07-10 | 株式会社カネカ | Lead frame for optical semiconductor, resin molded article for optical semiconductor and method of manufacturing the same, optical semiconductor package and optical semiconductor device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5029672A (en) * | 1973-07-17 | 1975-03-25 |
-
1983
- 1983-05-23 JP JP58089103A patent/JPS5910251A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5029672A (en) * | 1973-07-17 | 1975-03-25 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5910251A (en) | 1984-01-19 |
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