KR0152943B1 - Lead frame and semiconductor package - Google Patents

Lead frame and semiconductor package

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Publication number
KR0152943B1
KR0152943B1 KR1019950022836A KR19950022836A KR0152943B1 KR 0152943 B1 KR0152943 B1 KR 0152943B1 KR 1019950022836 A KR1019950022836 A KR 1019950022836A KR 19950022836 A KR19950022836 A KR 19950022836A KR 0152943 B1 KR0152943 B1 KR 0152943B1
Authority
KR
South Korea
Prior art keywords
lead
lead frame
paddle
semiconductor chip
semiconductor package
Prior art date
Application number
KR1019950022836A
Other languages
Korean (ko)
Other versions
KR970008539A (en
Inventor
송치중
Original Assignee
문정환
엘지반도체주식회사
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Application filed by 문정환, 엘지반도체주식회사 filed Critical 문정환
Priority to KR1019950022836A priority Critical patent/KR0152943B1/en
Publication of KR970008539A publication Critical patent/KR970008539A/en
Application granted granted Critical
Publication of KR0152943B1 publication Critical patent/KR0152943B1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H01L23/49551—Cross section geometry characterised by bent parts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49565—Side rails of the lead frame, e.g. with perforations, sprocket holes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

본 발명은 리드 프레임 및 반도체 패키지에 관한 것으로, 종래의 반도체 패키지는 작동시 리드 프레임의 아웃 리드로만 열방출이 이루어져 크랙, 파손 등의 신뢰성이 저하되는 문제점이 있었고, 이러한 문제점을 해결하기 위하여 리드의 일정부분과 패들을 이엠시의 상·하면에 위치하도록 리드 프레임을 제작하는데 제작상의 어려운 문제점이 있었던 바, 본 발명은 리드를 갖는 리드부(10)와, 반도체 칩(22)이 고정 부착되는 패들(24)을 갖는 패들부(24)를 분리 형성하여서 된 리드 프레임 및 이엠시(26)의 상·하 면에 리드(12)와 패들(24)을 각각 노출시켜 열방출이 용이하도록 함으로써 후공정에서의 신뢰성을 향상시킨 반도체 패키지에 관한 것이다.The present invention relates to a lead frame and a semiconductor package, the conventional semiconductor package has a problem that the heat is discharged only to the out lead of the lead frame during operation has a problem that the reliability, such as cracks, breakage, etc. is reduced, in order to solve such a problem There was a difficult manufacturing problem in manufacturing a lead frame so that a predetermined portion and the paddles are located on the upper and lower surfaces of the EMS, the present invention provides a paddle in which the lead portion 10 having the lead and the semiconductor chip 22 are fixedly attached. The post-process by exposing the lead 12 and the paddle 24 to the upper and lower surfaces of the lead frame and the EMSC 26 by separately forming the paddle portion 24 having the 24 to facilitate heat dissipation. The present invention relates to a semiconductor package having improved reliability.

Description

리드 프레임 및 반도체 패키지Lead Frame and Semiconductor Packages

제1도는 종래 리드 프레임의 구조를 보인 평면도.1 is a plan view showing the structure of a conventional lead frame.

제2도는 종래 반도체 패키지의 구성을 보인 종단면도.2 is a longitudinal sectional view showing the structure of a conventional semiconductor package.

제3도는 본 발명 복합 리드 프레임의 구성을 설명하기 위한 개략사시도.Figure 3 is a schematic perspective view for explaining the configuration of the composite lead frame of the present invention.

제4도는 본 발명 반도체 패키지의 구성을 보인 종단면도.Figure 4 is a longitudinal cross-sectional view showing the configuration of the semiconductor package of the present invention.

제5도는 제4도의 다른 실시예를 보인 종단면도.Figure 5 is a longitudinal cross-sectional view showing another embodiment of FIG.

제6도는 제4도의 또다른 실시예를 보인 종단면도.6 is a longitudinal sectional view showing yet another embodiment of FIG.

제7도는 제4도의 또다른 실시예를 보인 종단면도.7 is a longitudinal sectional view showing another embodiment of FIG.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

10 : 리드부 11,11',21,21' : 사이드레일10: lead portion 11, 11 ', 21, 21': side rail

12 : 리드 12a : 노출부12: lead 12a: exposed part

12b : 접속부 13 : 댐바12b: connection portion 13: dam bar

20 : 패들부 22 : 반도체 칩20: paddle portion 22: semiconductor chip

23 : 타이 바 24 : 패들23: tie bar 24: paddle

25 : 와이어 26 : 이엠시25: Wire 26: Emsey

본 발명은 리드 프레임 및 반도체 패키지에 관한 것으로, 특히 리드의 소정부분이 이엠시의 상면에 노출되고, 패들이 이엠시의 하면에 노출되도록 하여 열방출이 용이하도록 한 리드 프레임 및 반도체 패키지에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a lead frame and a semiconductor package, and more particularly, to a lead frame and a semiconductor package in which a predetermined portion of the lead is exposed to the top surface of the emsi and the paddle is exposed to the bottom surface of the emsi so that heat dissipation is easy. .

제1도는 종래 리드 프레임의 구조를 보인 평면도이고, 제2도는 종래 반도체 패키지의 구성을 보인 종단면도로서, 이를 참조하여 일반적인 반도체 패키지의 제조과정을 살펴보면 다음과 같다.FIG. 1 is a plan view showing a structure of a conventional lead frame, and FIG. 2 is a longitudinal cross-sectional view showing a structure of a conventional semiconductor package. Referring to this, a manufacturing process of a general semiconductor package is as follows.

먼저, 리드 프레임의 구조를 살펴본다.First, the structure of the lead frame will be described.

일반적인 종래 리드 프레임(1)은 제1도에 도시되어 있는 바와 같이, 양측 사이드 레일(1a)(1b)의 내측 중간부에 타이 바(2a)로 패들(2)이 지지되어 있고, 그 패들(2)의 양측에 수개의 인너 리드(4)가 댐바(4a)에 의해 지지되어 있으며, 상기 인너 리드(4)에 아웃 리드(7)가 일체로 연결설치되어 있는 것이다.As shown in FIG. 1, a conventional conventional lead frame 1 has a paddle 2 supported by a tie bar 2a at an inner middle portion of both side rails 1a and 1b, and the paddle ( Several inner leads 4 are supported by the dam bars 4a on both sides of 2), and the out leads 7 are integrally connected to the inner leads 4.

또한, 상기와 같은 리드 프레임(1)을 이용하여 제조된 종래의 반도체 패키지는 제2도에 도시하고 있는 바와 같이, 리드 프레임(1)의 패들(2)위에 반도체 칩(3)이 부착되어 있고, 그 반도체 칩(3)의 양측에 수개의 인너 리드(4)가 배열되어 있으며, 상기 반도체 칩(3)과 인너 리드(4)는 와이어(5)로 전기적인 접속이 이루어져 있고, 상기 반도체 칩(3), 인너 리드(4), 와이어(5)를 포함하는 일정면적이 이엠시(EMC:EPOXY MOLDING COMPUND)(6)로 몰딩되어 있을뿐 아니라, 상기 인너 리드(4)에는 이엠시(6)의 외부로 아웃리드(7)가 연결 설치되어 있는 것이다.In addition, in the conventional semiconductor package manufactured using the lead frame 1 as described above, as shown in FIG. 2, the semiconductor chip 3 is attached to the paddle 2 of the lead frame 1. Several inner leads 4 are arranged on both sides of the semiconductor chip 3, and the semiconductor chip 3 and the inner lead 4 are electrically connected to each other by a wire 5. (3), the constant area including the inner lead 4 and the wire 5 is not only molded into an EMPO (EPOXY MOLDING COMPUND) 6, and the inner lead 4 has an imsi 6 formed therein. The outlead 7 is connected to the outside.

상기와 같은 리드 프레임(1)을 이용하여 종래의 반도체 패키지를 제조하는 순서를 설명하면 다음과 같다.The procedure for manufacturing a conventional semiconductor package using the lead frame 1 as described above is as follows.

리드 프레임(1)의 패들(2)을 인너 리드(4)면보다 약간 내리는 다운 셋팅을 수행하는 단계와, 상기 패들(2)의 상부에 반도체 칩(3)을 부착하는 다이 본딩 공정을 수행하는 단계와, 상기 반도체 칩(3)과 인너 리드(4)를 와이어(5)로 연결하는 와이어 본딩 공정을 수행하는 단계와, 상기 반도체 칩(3), 인너 리드(4), 와이어(5)를 포함하는 일정면적을 이엠시(6)로 몰딩하는 단계와, 상기 타이 바(2a), 댐바(4a), 정크부의 플래시등을 제거하는 트리밍 공정 및 상기 아웃 리드(7)를 소정의 형태로 절곡하는 포밍 공정을 수행하는 단계의 순서로 반도체 패키지가 제조되는 것이다.Performing down setting of the paddle 2 of the lead frame 1 slightly lower than the inner lead 4 surface, and performing a die bonding process of attaching the semiconductor chip 3 to the top of the paddle 2. And performing a wire bonding process for connecting the semiconductor chip 3 and the inner lead 4 with a wire 5, and including the semiconductor chip 3, the inner lead 4, and the wire 5. Molding a predetermined area to the EMSC 6, a trimming process of removing the tie bar 2a, the dam bar 4a, the flash of the junk part, and the bending of the out lead 7 into a predetermined shape. The semiconductor package is manufactured in the order of performing the forming process.

그러나, 상기와 같은 종래의 반도체 패키지는 작동시 패키지 내부에서 발생하는 열이 리드 프레임(1)의 아웃 리드(7)로만 열방출이 이루어져 후공정에서 패키지의 크랙 또는 오동작이 발생하여 그로 인한 신뢰성이 저하되는 문제점이 있었고, 또 상기와 같은 문제점의 해결을 위하여 열방출이 잘되도록 리드 프레임(1)의 패들(2)과 인너 리드(4)를 이엠시(6)의 외부로 노출시키는데 제작상의 어려운 문제점이 있었다.However, in the conventional semiconductor package as described above, the heat generated inside the package during operation is only released to the out lead 7 of the lead frame 1, so that a crack or malfunction of the package occurs in a later process, resulting in high reliability. In order to solve the problems described above, the paddle 2 and the inner lead 4 of the lead frame 1 are exposed to the outside of the EMSC 6 so that the heat is released well. There was a problem.

이를 감안하여 안출한 본 발명의 목적은 리드 프레임의 리드와 패들이 패키지 제조시 이엠시의 외부로 노출이 용이한 리드 프레임을 제공함에 있다.In view of this, an object of the present invention is to provide a lead frame in which the lead and paddle of the lead frame can be easily exposed to the outside of the EMSI when manufacturing a package.

본 발명의 다른 목적은 패키지의 작동시 패키지의 외부로 열방출이 잘되는 반도체 패키지를 제공함에 있다.It is another object of the present invention to provide a semiconductor package that has good heat dissipation to the outside of the package during operation of the package.

상기와 같은 본 발명의 목적을 달성하기 위하여 반도체 칩과 와이어 본딩되는 리드를 갖는 리드부와, 반도체 칩이 고정부착되는 패들을 갖는 패들부를 분리 형성하여서 구성된 것을 특징으로 하는 리드 프레임과; 리드 프레임의 패들위에 반도체 칩이 부착되어 있고, 그 반도체 칩과 리드가 와이어로 접속되어 있으며, 상기 반도체 칩, 리드, 와이어를 포함하는 일정면적이 이엠시로 몰딩되어 있는 반도체 패키지에 있어서, 상기 리드의 소정부위를 상측으로 절곡하여 이엠시의 상면에 노출되도록 설치하고, 상기 패들을 다운-셋팅하여 이엠시의 하면에 노출이 되도록 설치하여 구성한 것을 특징으로 하는 반도체 패키지가 제공된다.In order to achieve the object of the present invention as described above, a lead frame comprising a lead portion having a lead bonded to the semiconductor chip and a paddle portion having a paddle to which the semiconductor chip is fixedly attached; A semiconductor package, wherein a semiconductor chip is attached to a paddle of a lead frame, the semiconductor chip and a lead are connected by wire, and a predetermined area including the semiconductor chip, the lead, and the wire is molded with an EMS. The semiconductor package is provided by bending a predetermined portion of the upper side to be installed so as to be exposed to the upper surface of the emsi, and down-setting the paddle so as to be exposed to the lower surface of the emsi.

이하, 상기와 같이 구성되어 있는 본 발명의 리드 프레임과 반도체 패키지를 첨부된 도면에 의거하여 보다 상세히 설명한다.Hereinafter, the lead frame and the semiconductor package of the present invention configured as described above will be described in more detail with reference to the accompanying drawings.

제3도는 본 발명 리드 프레임의 구성을 설명하기 위한 개략사시도이고, 제4도는 본 발명 반도체 패키지의 구성을 보인 종단면도이다.3 is a schematic perspective view for explaining the configuration of the lead frame of the present invention, and FIG. 4 is a longitudinal sectional view showing the structure of the semiconductor package of the present invention.

먼저, 본 발명의 리드 프레임을 설명한다.First, the lead frame of this invention is demonstrated.

제3도에 도시한 바와 같이, 본 발명의 리드 프레임은 리드부(10)와 패들부(20)가 분리 형성되어 있다.As shown in FIG. 3, in the lead frame of the present invention, the lead portion 10 and the paddle portion 20 are formed separately.

상기 리드부(10)는 양측 사이드레일(11)(11')의 내측으로 수개의 리드(12)가 댐바(13)에 의해 지지되어 설치되고, 그 리드(12)는 상부로 절곡되어 이엠시(도시되어 있지 않음)의 상면에 노출되는 노출부(12a)와, 그 노출부(12a)에서 내측하부로 절곡되어 와이어(도시되어 있지 않음)가 접속되는 접속부(12b)로 구성되어 있는 것이다.The lid part 10 is provided with several leads 12 supported by the dam bars 13 to the inside of both side rails 11 and 11 ′, and the leads 12 are bent upwards to form an EMS. It is comprised from the exposed part 12a exposed to the upper surface of (not shown), and the connection part 12b bent from the exposed part 12a to the inner side lower part, and the wire (not shown) connected.

또한, 상기 패들부(20)는 양측 사이드레일(21)(21')의 내측에 반도체 칩(22)이 부착되며 타이 바(23)로 지지되어 있는 패들(24)이 하측으로 다운-셋팅되어 있는 것이다.In addition, the paddle portion 20 has a semiconductor chip 22 attached to both sides of the side rails 21 and 21 ′, and the paddle 24 supported by the tie bars 23 is down-set downward. It is.

제4도에 도시한 바와 같이, 본 발명의 반도체 패키지는 패들(24)위에 반도체 칩(22)이 부착되어 있고, 그 반도체 칩(22)의 양측에 수개의 리드(12)가 배열되어 있으며, 상기 반도체 칩(22)과 각각의 리드(12)는 와이어(25)로 연결되어 있을뿐 아니라, 상기 반도체 칩(22), 리드(12), 와이어(25)를 포함하는 일정면적이 이엠시(26)로 몰딩되어 있는 반도체 패키지 구조에 있어서, 상기 리드(12)의 소정부위를 상측으로 절곡하여 이엠시(26)의 상면에 노출되도록 설치하고, 상기 패들(24)을 다운-셋팅하여 이엠시(26)의 하면에 노출이 되도록 설치하여 열방출의 경로가 되도록 한 것을 특징으로 한다.As shown in FIG. 4, in the semiconductor package of the present invention, the semiconductor chip 22 is attached on the paddle 24, and several leads 12 are arranged on both sides of the semiconductor chip 22. The semiconductor chip 22 and each lead 12 are not only connected to the wire 25, but also have a predetermined area including the semiconductor chip 22, the lead 12, and the wire 25. In the semiconductor package structure molded in 26, a predetermined portion of the lead 12 is bent upward to be exposed to an upper surface of the EMS 26, and the paddle 24 is down-set to establish an EMS. It is characterized in that the lower surface of (26) is provided so as to be exposed so that the path of heat release.

상기와 같은 본 발명의 리드 프레임과 그 리드 프레임을 이용한 반도체 패키지의 제조하는 방법을 순서에 의거하여 살펴보면 다음과 같다.Looking at the lead frame of the present invention as described above and a method of manufacturing a semiconductor package using the lead frame in the following order.

상기 패들부(20)의 패들(24)에 반도체 칩(22)을 부착하는 다이본딩 공정을 수행하는 단계와, 상기 리드 프레임의 리드부(10)와 패들부(20)를 용접 혹은 리벳팅으로 접합하는 접합공정을 수행하는 단계로 리드 프레임이 제조되고; 상기 리드 프레임의 패들(24)에 부착되어 있는 반도체 칩(22)과 리드(12)를 와이어(25)로 전기적인 접속을 하는 와이어 본딩 공정을 수행하는 단계와, 상기 반도체 칩(22), 리드(12), 와이어(25)를 포함하는 일정면적을 이엠시(26)로 몰딩하는 몰딩 단계를 수행함으로써 비로소 본 발명의 반도체 패키지가 완성되는 것이다.Performing a die bonding process of attaching the semiconductor chip 22 to the paddle 24 of the paddle portion 20, and welding or riveting the lead portion 10 and the paddle portion 20 of the lead frame. A lead frame is manufactured in a step of performing a joining process for joining; Performing a wire bonding process for electrically connecting the semiconductor chip 22 and the lead 12 attached to the paddle 24 of the lead frame with the wire 25, and the semiconductor chip 22 and the lead. (12), the semiconductor package of the present invention is completed by performing a molding step of molding a predetermined area including the wire 25 into the EMS 26.

이와 같이 제조되는 반도체 패키지는 이엠시(26)의 상면에 리드(12)의 일정부분이 외부로 노출되도록 노출부(12a)가 형성되고, 패들(24)이 이엠시(26)의 하면에 외부로 노출이 되도록 설치되어 패키지 작동시 외부로의 열방출 경로가 되는 것이다.In the semiconductor package manufactured as described above, an exposed portion 12a is formed on the top surface of the emsi 26 so that a predetermined portion of the lid 12 is exposed to the outside, and the paddle 24 is external to the lower surface of the emsi 26. It is installed so as to be exposed to the furnace, and it becomes a heat dissipation path to the outside during package operation.

제5도는 제4도의 다른 실시예를 보인 것으로 리드(12)의 외부로 아웃 리드(30)를 연장형성한 것이고, 제6도는 제4도의 또다른 실시예를 보인 것으로 리드(12)를 반도체 칩(22)의 상면에 얹혀지도록 하는 LOC(LEAD ON CHIP)형태로써 패키지를 소형화시킬 수 있으며, 제7도는 제4도의 또다른 실시예를 보인 것으로 LOC형태의 패키지 리드(12)에 아웃 리드(30가 패키지의 외부로 연장형성된 실시예를 보인 것이다.FIG. 5 shows another embodiment of FIG. 4 to extend the out lead 30 to the outside of the lead 12. FIG. 6 shows another embodiment of FIG. The package can be miniaturized in the form of a lead on chip (LOC) to be mounted on an upper surface of the 22, and FIG. 7 shows another embodiment of FIG. Shows an embodiment extended to the outside of the package.

이상에서 상세히 설명한 바와 같이 본 발명의 리드 프레임은 리드부와 패들부를 별도로 분리 형성하여 접합함으로써 리드의 일정부분이 패키지 제조시 이엠시의 상면에 위치하고, 패들이 이엠시의 하면에 위치하도록 제조하는데 용이한 효과가 있으며, 상기 리드 프레임을 이용하여 제조된 본 발명의 반도체 패키지는 이엠시의 상·하면에 각각 리드의 노출부와 패들이 외부로 노출되어 있어, 패키지 작동시 열방출경로가 되도록 함으로써 후공정에서 패키지의 크랙 및 파손을 방지하는 등의 신뢰성이 향상되는 효과가 있는 것이다.As described in detail above, the lead frame of the present invention is easily formed by separately forming and joining the lead portion and the paddle portion so that a predetermined portion of the lead is positioned on the top surface of the EMS, and the paddle is located on the bottom surface of the EMS. According to the present invention, the semiconductor package of the present invention manufactured using the lead frame has exposed portions and paddles of the leads on the upper and lower surfaces of the EMSC to the outside, so that the heat dissipation path during the package operation is achieved. In the process, there is an effect of improving reliability, such as preventing cracks and breakage of the package.

Claims (4)

반도체 칩과 와이어 본딩되는 리드를 갖는 리드부와, 반도체 칩이 고정 부착되는 패들을 갖는 패들부를 분리 형성하여서 된 것을 특징으로 하는 리드 프레임.And a paddle portion having a lead portion having a lead bonded to the semiconductor chip and a paddle portion to which the semiconductor chip is fixedly attached. 제1항에 있어서, 상기 리드부는 양측 사이드레일의 내측으로 다수개의 리드가 댐바에 의해 지지되어 설치되고, 그 리드는 상부로 절곡되어 이엠시의 상면에 노출되는 노출부와 그 노출부에서 내측하부로 절곡되어 와이어가 접속되는 접속부로 구성되어 있는 것을 특징으로 하는 리드 프레임.According to claim 1, wherein the lead portion is provided with a plurality of leads are supported by the dam bar in the inner side of both side rails, the lead is bent upward and exposed to the upper surface of the emsi and the inner lower portion from the exposed portion A lead frame, wherein the lead frame is bent to form a connection portion to which a wire is connected. 제1항에 있어서, 상기 하측 패들부는 양측 사이드레일의 내측에 반도체 칩이 부착되는 패들이 타이 바로 지지되어 하측으로 다운-셋팅되어 있는 것을 특징으로 하는 리드 프레임.The lead frame according to claim 1, wherein the lower paddle portion is supported by paddles to which a semiconductor chip is attached to the inside of both side rails and down-set downward. 패들위에 반도체 칩이 부착되어 있고, 그 반도체 칩과 리드가 와이어로 접속되어 있으며, 상기 반도체 칩, 리드, 와이어를 포함하는 일정 면적이 이엠시로 몰딩되어 있는 반도체 패키지에 있어서, 상기 리드의 소정부위를 상측으로 절곡하여 이엠시의 상면에 노출되도록 설치하고, 상기 패들을 다운-셋팅하여 이엠시의 하면에 노출이 되도록 설치하여 구성한 것을 특징으로 하는 반도체 패키지.In a semiconductor package having a semiconductor chip attached to a paddle, the semiconductor chip and a lead are connected by wire, and a predetermined area including the semiconductor chip, the lead, and the wire is molded with an EMS. Is installed to be exposed to the upper surface of the emsey by bending to the upper side, and down-set the paddle and installed so as to be exposed on the lower surface of the emsey.
KR1019950022836A 1995-07-28 1995-07-28 Lead frame and semiconductor package KR0152943B1 (en)

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