KR970008539A - Lead Frame and Semiconductor Packages - Google Patents

Lead Frame and Semiconductor Packages Download PDF

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Publication number
KR970008539A
KR970008539A KR1019950022836A KR19950022836A KR970008539A KR 970008539 A KR970008539 A KR 970008539A KR 1019950022836 A KR1019950022836 A KR 1019950022836A KR 19950022836 A KR19950022836 A KR 19950022836A KR 970008539 A KR970008539 A KR 970008539A
Authority
KR
South Korea
Prior art keywords
lead
lead frame
paddle
semiconductor chip
exposed
Prior art date
Application number
KR1019950022836A
Other languages
Korean (ko)
Other versions
KR0152943B1 (en
Inventor
송치중
Original Assignee
문정환
Lg 반도체 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 문정환, Lg 반도체 주식회사 filed Critical 문정환
Priority to KR1019950022836A priority Critical patent/KR0152943B1/en
Publication of KR970008539A publication Critical patent/KR970008539A/en
Application granted granted Critical
Publication of KR0152943B1 publication Critical patent/KR0152943B1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H01L23/49551—Cross section geometry characterised by bent parts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49565—Side rails of the lead frame, e.g. with perforations, sprocket holes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

본 발명은 리드 프레임 및 반도체 패키지에 관한 것으로, 종래의 반도체 패키지는 작동시 리드 프레임의 아웃 리드로만열방출이 이루어져 크랙, 파손 등의 신뢰성이 저하되는 문제점이 있었고, 이러한 문제점을 해결하기 위하여 리드의 일정부분과 패들을 이엠시의 상,하면에 위치하도록 리드 프레임을 제작하는데 제작상의 어려운 문제점이 있었던 바, 본 발명은 리드를 갖는 리드부(10)와, 반도체 칩(22)이 고정 부착되는 패들(24)을 갖는 패들부(24)를 분리 형성하여서 된 리드프레임 및 이엠시(26)의 상,하 면에 리드(12)와 패들(24)을 각각 노출시켜 열방출이 용이하도록 함으로써 후공정에서의 신뢰성을 향상시킨 반도체 패키지에 관한 것이다.The present invention relates to a lead frame and a semiconductor package, the conventional semiconductor package has a problem that the heat discharge is generated only by the out lead of the lead frame during operation, the reliability of cracks, breakage, etc. is reduced, in order to solve such a problem There was a difficult manufacturing problem in manufacturing a lead frame so that a predetermined portion and the paddles are positioned on the upper and lower surfaces of the EMSC. In the present invention, the lead portion 10 having the lead and the paddle to which the semiconductor chip 22 is fixedly attached The post-process by exposing the leads 12 and the paddles 24 on the upper and lower surfaces of the lead frame and the EMSC 26 by separately forming the paddle portion 24 having the 24 to facilitate heat dissipation. The present invention relates to a semiconductor package having improved reliability.

Description

리드 프레임 및 반도체 패키지Lead Frame and Semiconductor Packages

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도는 본 발명 복합 리드 프레임의 구성을 설명하기 위한 개략사시도, 제4도는 본 발명 반도체 패키지의 구성을 보인 종단면도.Figure 3 is a schematic perspective view for explaining the configuration of the composite lead frame of the present invention, Figure 4 is a longitudinal cross-sectional view showing the configuration of the semiconductor package of the present invention.

Claims (4)

반도체 칩과 와이어 본딩되는 리드를 갖는 리드부와, 반도체 칩이 고정 부착되는 패들을 갖는 패들부를 분리 형성하여서 된 것을 특징으로 하는 리드 프레임.And a paddle portion having a lead portion having a lead bonded to the semiconductor chip and a paddle portion to which the semiconductor chip is fixedly attached. 제1항에 있어서, 상기 리드부는 양측 사이드레일의 내측으로 다수개의 리드가 댐바에 의해 지지되어 설치되고, 그 리드는 상부로 절곡되어 이엠시의 상면에 노출되는 노출부와 그 노출부에서 내측하부로 절곡되어 와이어가 접속되는 접속부로 구성되어 있는 것을 특징으로 하는 리드 프레임.According to claim 1, wherein the lead portion is provided with a plurality of leads are supported by the dam bar in the inner side of both side rails, the lead is bent upward and exposed to the upper surface of the emsi and the inner lower portion from the exposed portion A lead frame, wherein the lead frame is bent to form a connection portion to which a wire is connected. 제1항에 있어서, 상기 하측 패들부는 양측 사이드레일의 내측에 반도체 칩이 부착되는 패들이 타이 바로지지되어 하측으로 다운-셋팅되어 있는 것을 특징으로 하는 리드 프레임.The lead frame according to claim 1, wherein the lower paddle portion has a paddle to which a semiconductor chip is attached to the inner side of both side rails and is down-set downward by a tie bar. 패들위에 반도체 칩이 부착되어 있고, 그 반도체 칩과 리드가 와이어로 접속되어 있으며, 상기 반도체 칩, 리드, 와이어를 포함하는 일정 면적이 이엠시로 몰딩되어 있는 반도체 패키지에 있어서, 상기 리드의 소정부위를 상측으로 절곡하여 이엠시의 상면에 노출되도록 설치하고, 상기 패들을 다운-셋팅하여 이엠시의 하면에 노출이 되도록 설치하여 구성한 것을 특징으로 하는 반도체 패키지.In a semiconductor package having a semiconductor chip attached to a paddle, the semiconductor chip and a lead are connected by wire, and a predetermined area including the semiconductor chip, the lead, and the wire is molded with an EMS. Is installed to be exposed to the upper surface of the emsey by bending to the upper side, and down-set the paddle and installed so as to be exposed on the lower surface of the emsey. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950022836A 1995-07-28 1995-07-28 Lead frame and semiconductor package KR0152943B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950022836A KR0152943B1 (en) 1995-07-28 1995-07-28 Lead frame and semiconductor package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950022836A KR0152943B1 (en) 1995-07-28 1995-07-28 Lead frame and semiconductor package

Publications (2)

Publication Number Publication Date
KR970008539A true KR970008539A (en) 1997-02-24
KR0152943B1 KR0152943B1 (en) 1998-10-01

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950022836A KR0152943B1 (en) 1995-07-28 1995-07-28 Lead frame and semiconductor package

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KR (1) KR0152943B1 (en)

Also Published As

Publication number Publication date
KR0152943B1 (en) 1998-10-01

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