KR940027490A - Frequency discrimination method of monitor and its compensation circuit - Google Patents

Abstract

The present invention relates to a frequency discrimination method of a monitor and a compensation circuit thereof, and a conventional counter counts the number of horizontal synchronization signals (H-SYNC) in the vertical synchronization signal (V-SYNC), so that the horizontal frequency (31.5KHZ) / The vertical frequency (70HZ) and the horizontal frequency (38kHZ) / vertical frequency (84HZ) show almost the same value, which can cause a malfunction. When the mode is selected, the mode control signals are “high” and “low”. By outputting only, it requires a lot of parts when connecting with analog, and it has the disadvantage that ASIC cannot be composed by using only resistor and capacitor.

Therefore, in order to solve the conventional problems, the present invention classifies and identifies multiple synchronization signals, automatically corrects deviations according to the synchronization signals, and adopts various output methods to bring productivity and reliability to the logic gate. There is an effect that can be configured and ASIC.

Description

Frequency discrimination method of monitor and its compensation circuit

Since this is an open matter, no full text was included.

FIG. 2 is a frequency discrimination and compensation circuit diagram of the present invention monitor, FIG. 3 is a detailed circuit diagram of a horizontal synchronous control section, FIG. 4 is a detailed circuit diagram of a horizontal synchronous signal polarity discriminating section, and FIG. Fig. 4 is an input / output waveform diagram of each part.

Claims (19)

The polarity of the horizontal sync signal H-SYNC input is determined, and the horizontal sync controller 11 outputs a frequency having a constant polarity at all times and the polarity of the vertical sync signal V-SYNC. In addition, the frequency is outputted to the vertical synchronous control unit 12 and the horizontal and vertical synchronous control unit 11, 12 to always make a constant frequency and output the oscillator clock frequency (3.58MHZ) and the frequency difference Generation of horizontal and vertical pulses to make a duty ratio of the horizontal and vertical frequency counters 13 and 14 and the horizontal and vertical frequency counters 13 and 14 to generate a duty ratio according to the frequency output from the horizontal and vertical frequency counters 13 and 14. Combining the input signals with the horizontal and vertical controllers 17 and 18 which classify the desired frequency bands by combining the units 15 and 16, the outputs of the horizontal and vertical frequency counters 15 and 16, respectively. Display mode (DISPL) AY MODE) and the mode controller 19 for outputting a mode signal corresponding thereto, and the polarity of the horizontal and vertical frequency counter 14 and the horizontal and vertical controllers 17 and 18 are inputted to change the frequency. Or a mute pulse generator 20 for outputting a pulse to mute a predetermined time when the frequency polarity changes, and horizontal and vertical frequency counters 13 and 14 horizontally with the horizontal and vertical synchronous control units 11 and 12. And an output selector 21 for inputting signals output from the vertical pulse generators 15 and 16 and the mode controller 19 and selecting and outputting the outputs according to the selection of the output mode OM. Abacus plate discrimination and compensation circuit of the monitor consisting of an oscillator 23 oscillating in accordance with the clock. The horizontal synchronous signal polarity discrimination unit 111 according to claim 1, wherein the horizontal synchronous control unit 11 determines a polarity of the input horizontal synchronous signal H-SYNC and outputs a horizontal synchronous polarity signal P _H. ), And the horizontal synchronous signal polarity discrimination unit 111 receives the horizontal synchronous polarity signal P _H and the horizontal synchronous signal H-SYNC, respectively, to output a frequency having a constant polarity. Frequency discrimination and compensation circuit of the monitor, characterized in that composed of an OA gate (XOR1). 3. The first deflip according to claim 2, wherein the horizontal synchronizing signal polarity discriminating unit 111 supplies a high pulse for a certain period for each rising edge of the horizontal synchronizing signal H-SYNC applied to the clock terminal. A flop DF1, an AND gate ADl for supplying a clock until the first dip-flop DF1 is reset by the AND gate AD2, and a clock input through the AND gate AD1 is predetermined. Outputs a counter 112 that counts by frequency, an AND gate AD4 that detects the level of the output pulse of the counter 112 after a predetermined time, and a clock pulse corresponding to the output level of the AND gate AD4. A second deflip-flop DF2 and an output pulse of the second deflip-flop DF2 as a clock to output a horizontal synchronous polarity signal P _H opposite to the horizontal synchronous signal H-SYNC. Inverted output and reset signal of the third deflip flop DF3 and the second deflip flop DF2 And an AND gate (AD2) (AD3) for outputting a signal for clearing with the first deflip-flop (DF1) and the counter (112) by AND combining the signals. The frequency discrimination and compensation circuit of a monitor according to claim 1, wherein the vertical synchronization controller (12) has the same principle and configuration as the horizontal synchronization controller (11). The horizontal pulse generator (15) includes: an 8-bit counter (151) for counting the basic clock (CK), an output (Q ' _0- Q' ₆ ) of the 8-bit counter (151), and Noar gates NR1 for noring the outputs Q ₀ -Q ₆ of the horizontal frequency counter 13, outputs Q ′ ₀ -Q ' ₆ of the 8-bit counter 151, and the horizontal frequency counter ( An oragate OR3 that receives the output of the exclusive oracle XR1-XR7 that exclusively rings the outputs Q ₀ -Q ₆ of 13), and the noagate that is input to the data input terminal. And thirteenth and fourteenth flip-flops DF13 and DF14 for synchronizing and outputting the oragate NR1 and OR3 to a clock, and the thirteenth D inputting a clock terminal with " 1 " The fifteenth flip-flop by AND-combining the fifteenth flip-flop DF15 outputted in synchronization with the output of the flip-flop DF13, and the output of the reset signal RESET and the fourteenth flip-flop DF14. (DF15) That consists of the AND gate (AD12) for outputting the set of terminals to determine the frequency of the monitor, characterized, and a compensation circuit. The method of claim 1, wherein the output selector 21 receives the specified external signal according to the frequency so that the address and control value can be received and selectable when the pulse width controller 22 is further configured to adjust the pulse width. Frequency discrimination and compensation circuit of monitor. The method of claim 7, wherein the pulse width control unit 22 receives the external signal specified according to the frequency and outputs the address (A _0- A ₂ ) corresponding to the external data according to the frequency and A clock generator 223 for logically combining the counter output to generate a clock pulse, a demultiplexer 224 for selecting an output by changing an address according to the output of the clock generator 223, and the clock according to the input clock And a pulse width adjusting unit (223) for adjusting the pulse width by an input output from the demultiplexer (224). 8-bit counter 131 for counting 8 bits of the input clock CK as one cycle, and one cycle count for outputting the enable and disable signals so that the 8-bit counter 131 counts once every two cycles. Setting unit 130, the first and second latch unit 132, 133 to sequentially latch the output of the 8-bit counter 131 for a predetermined time, and the first and second latch unit 132, 133 The output of the input is inverted, and either input is inverted and inputted, and then the difference between the main clock frequency through the 8-bit full adder 134 and the 8-bit full adder 134 is equal to or less than one. When the back surface is prevented from being loaded on the second flip flop 133, and when there is a difference of two or more, the first flip flop 132 is newly loaded on the second flip flop 133 and the frequency is changed. Frequency counter circuit consisting of a frequency change detection unit 135 for outputting a signal (HT). 10. The apparatus of claim 8, wherein the one cycle count setting unit 130 adjusts the pulse width of the input applied to the data input terminal using the input synchronization signal as a clock and outputs the non-inverted output of the flip-flop. And an AND gate in which a counter is counted once every two periods by combining and a reset signal (RESET). The frequency change detection unit (135) of claim 8, wherein the frequency change detection unit (135) outputs a 7-bit output of the 8-bit full adder (134) and a carry out output of the 8-bit full adder (134) through the inverter (13). 7 exclusive oragates (XOR3-XOR9) for receiving the difference value, an oragate (OR1) for adding the outputs of the exclusive oragate (XOR3-XOR9), and the oragate according to the clock. A second latch by supplying and blocking a clock according to the output of the eighth flip-flop DF8 for outputting a pulse having a predetermined width using the output of OR1 as a data input; A frequency counter circuit comprising an end gate AD9 for adjusting a hold state of the unit 132. 10. The method of claim 8, wherein the exclusive orifice XOR3-XOR9 is the second latch portion 133 when the output value difference between the first latch portion 132 and the second latch portion 133 is 1 or 0. And the output of the first latch unit 132 is latched to the second latch unit 133 only when two or more latch signals are applied. An 8-bit counter 151 that counts the input 8-bit clock CK as one cycle, an output (Q ' _0- Q' ₆ ) of the 8-bit counter 151 and an output (QO-Q6) of the frequency counter. Count state comparison section 152 which compares values and detects only when the two values match and counts the flip-flop to a specific value in accordance with the cycle of the counter value of the 8-bit counter 151. And a duty adjusting section (154) for varying the duty according to the output of the frequency counter determined by the frequency of the synchronization signal. The count output comparison unit 152 receives an output of a frequency counter and an output of an 8-bit counter 151 that counts a clock, and receives the output of the frequency counter. Pulse generation circuit, characterized in that configured. The count state switching unit 153 combines each bit of the output of the 8-bit counter 151 and outputs the arrival state when the counter reaches a predetermined value. The OA gate OR3 which detects an output state by combining each bit of the output of the count output comparator 152 and the outputs of the NOA gate NR1 and the OR gate OR3 are respectively input to a data input terminal and clocked. And a thirteenth and fourteenth flip-flop (DF13) (DF14) for adjusting and outputting the pulse width according to the pulse width. The duty pulse controller 154 of claim 12, wherein the duty pulse adjusting unit 154 combines the output of the fourteenth flip-flop DF14 and the reset signal to generate and output an enable signal and a disable signal, and And a fifteenth flip-flop (DF15) for determining the pulse width according to the output of the AND gate (AD1) to adjust the duty. Horizontal and vertical synchronous signals that receive horizontal and vertical synchronous polarity signals (P _H ) (P _V ) and horizontal and vertical synchronous frequency change check signals (H _T ) (V _T ) respectively. A pulse change detection unit 201, a state control unit 202 for generating a screen mute signal when there is at least one change signal from the detection unit 201, and adjusting the state of the screen; and from the state control unit 202. A mute pulse generation circuit comprising a counting unit 203 which counts from that time when a mute signal is generated and returns to a previous state when a specific value is reached. 17. The apparatus of claim 16, wherein the horizontal and vertical synchronous pulse change detectors 201 detect the change of the horizontal and vertical synchronous polarity signals P _H (P _V ) input to the data input terminal in synchronization with a clock. A deflip-flop (DF19) (DF20), an output of the 19th and 20th flip-flop (DF19) (DF20), and the horizontal and vertical synchronous signals (P _H ) (P _V ), respectively, to receive a change signal. Exclusive oragate (XR19) (XR20) that detects and the output check signal of the exclusive oragate (XR19) (XR20) and the variable check signal (H _T ) (V _T ) of horizontal and vertical synchronization frequency A mute pulse generating circuit comprising an orifice (OR16) which is input to each and receives and outputs the signals. 17. The 21th flip-flop (DF21) for adjusting the screen mute time according to the change detection output of the horizontal and vertical synchronous pulse change detecting unit 201 to output a screen mute signal. And an AND gate AD60 for controlling the mute time of the twenty-first flip-flop DF21 according to the counter output of the 4-bit counter 205 through the inverter 127. . A first step of detecting and counting rising edge sections of the synchronization signal; and a second step of starting counting when the rising edge section is detected in the first step and detecting the level of the counted clock pulse after a predetermined time (T) has elapsed. And in the second step, if the level is high, the clock frequency is determined to be negative and outputs a low signal. If the level is low, the clock frequency is determined to be positive and outputs a high signal. How to determine the frequency of your monitor. ※ Note: This is to be disclosed by the original application.