KR100212650B1 - Method for discriminating frequency of monitor and compensating circuit thereof - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency discriminating method of a monitor and a compensation circuit thereof, and a conventional counter counts the number of horizontal synchronizing signals H _S in a vertical synchronizing signal V _S to obtain a horizontal frequency (31.5). ) / Vertical frequency (70 ) And horizontal frequency (38) ) / Vertical frequency (84 ) Can be malfunctioned by showing almost the same value.As the mode control signal is output as high (H) and low (L) only when the mode is selected, many parts are required when connecting with analog, and it is composed of only resistor and capacitor. It has a disadvantage that cannot be harmonized.

Therefore, in order to solve the conventional problems, the present invention classifies and identifies multiple synchronization signals, automatically corrects deviations according to the synchronization signals, and adopts various output methods to bring productivity and reliability to the logic gate. There is an effect that can be configured and ASIC.

Description

Frequency discrimination method of monitor and its compensation circuit

1 is a mode selection circuit diagram of a conventional monitor.

2 is a frequency discrimination and compensation circuit diagram of the monitor of the present invention.

3 is a detailed circuit diagram of the horizontal synchronous control unit in FIG. 2;

FIG. 4 is a detailed circuit diagram of the horizontal synchronous signal polarity discriminating part of FIG.

5 is an input / output waveform diagram of each part in FIG. 4;

6 is a detailed block diagram of a vertical synchronous control unit in FIG.

FIG. 7 is a detailed circuit diagram of the vertical synchronization signal polarity discriminating section in FIG.

8 is a detailed circuit diagram of a horizontal frequency counter in FIG.

9 is an input / output waveform diagram of each part in FIG. 8;

10 is a detailed circuit diagram of a vertical frequency counter in FIG.

FIG. 11 is a detailed circuit diagram of a horizontal pulse generator in FIG.

12 is a timing diagram of each part with respect to FIG.

FIG. 13 is a detailed circuit diagram of a vertical pulse generator in FIG.

FIG. 14 is a detailed circuit diagram of the horizontal control unit in FIG.

FIG. 15 is a detailed circuit diagram of the vertical control unit in FIG.

16 is a detailed circuit diagram of the mute pulse generator in FIG.

FIG. 17 is an input / output waveform diagram of parts of FIG. 16. FIG.

18 is a detailed circuit diagram of a mode control unit in FIG.

19 is a table of an output table for the vertical control unit in FIG.

FIG. 20 is a mode control table table for FIG. 18. FIG.

FIG. 21 is an address matching table table for FIG. 20. FIG.

FIG. 22 is a detailed circuit diagram of the pulse width control section in FIG.

23 is an output table table according to the mode classification in FIG.

24 is a timing diagram of each part with respect to FIG.

25 is a timing diagram of an embodiment with respect to FIG.

FIG. 26 is a detailed circuit diagram of an output selector in FIG.

* Explanation of symbols for main parts of the drawings

11: horizontal synchronous control unit 12: vertical synchronous control unit

13: horizontal frequency counter 14: vertical frequency counter

15: horizontal pulse generator 16: vertical pulse generator

17: horizontal control unit 18: vertical control unit

19: mode control unit 20: mute pulse generator

21: output selector 22: pulse width control unit

23: oscillation unit

The present invention relates to a frequency discrimination method for classifying and discriminating multiple synchronization signals output from a monitor or a terminal, and a compensation circuit thereof. In particular, classification of each frequency and pulse width modulation are performed to automatically correct deviations according to the synchronization signals. In addition, the present invention relates to a frequency discrimination method of a monitor and its compensation circuit, which achieves improved reliability and low cost by adopting various output methods.

In addition, the present invention can be designed as an integrated circuit in one chip by configuring the components of the frequency discrimination and compensation circuit as a logic circuit instead of using passive components such as resistors (R) and capacitors (C).

The mode selection circuit of a conventional monitor, as shown in FIG. 1, has a horizontal synchronous signal (I) input through a horizontal control unit 4 composed of a resistor R1, a capacitor C1, and an exclusive oar gate EOR1. H-SYNC) is a vertical synchronization signal input through a counter (1) for counting the input data, and through a vertical controller (5) consisting of a resistor (R2), a capacitor (C2), and an exclusive oragate (EOR2). V-SYNC) and a flip-flop (2) for synchronizing the input data and controlling the operation of the counter (1) with the synchronized data, and a mode control unit for selecting a mode according to the output state of the counter (1). It consists of (3).

Looking at the prior art configured as described above is as follows.

When the high level horizontal synchronous signal H-SYNC is input to the horizontal control unit 4, the high signal is charged to the capacitor C1 through the resistor R1, and thus is detected as low on the B side. The pulse of the high signal is output through the EOR1) and the voltage is discharged from the capacitor C1 when the horizontal synchronous signal of the low state is input. Therefore, a high signal is detected on the B side, and the high signal is generated through the exclusive OOR1. Pulse is output.

When the vertical control unit 5 is operated in the same manner as the horizontal control unit 4 and is input to the clock terminal of the flip-flop 2, the vertical control unit 5 is synchronized with the input vertical synchronization signal V-SYNC to The counter terminal 1 is controlled by controlling the reset terminal RS.

At this time, the horizontal synchronization signal H-SYNC input to the counter 1 operates as a clock and starts counting when the reset RESET is released, and outputs the counted value to the mode controller 3.

Then, the mode controller 3 selects a mode according to the input count value and outputs mode control signals M1, M2, M3, M4, and M5 corresponding thereto.

That is, the horizontal synchronous signal H-SYNC is counted for one period of the vertical synchronous signal V-SYNC, and the output value is sent to the mode controller 3 to output only the high (H) and the roll (L).

However, in the related art, the counter counts the number of horizontal synchronous signals H-SYNC in the vertical synchronous signal V-SYNC so that the horizontal frequency (31.5) is reached. ) / Vertical frequency (70 ) And horizontal frequency (38) ) / Vertical frequency (84 ) Shows almost the same value, and it can be malfunctioned.When mode is selected, the mode control signal is output as high (H) and roll (L) only. When using the vertical control unit, only resistors and capacitors (R1, C1) (R2, C2) are used.

Therefore, in order to solve the conventional problems, the present invention classifies and identifies multiple synchronization signals, automatically corrects deviations according to the synchronization signals, and adopts various output methods to bring productivity and reliability to the logic gate. Since it is configurable, a frequency discrimination method of a monitor and a compensation circuit thereof have been invented to enable ASIC, which will be described below in detail with reference to the accompanying drawings.

FIG. 2 is a frequency discrimination and compensation circuit diagram of the monitor of the present invention. As shown in FIG. 2, the polarity of the horizontal synchronization signal H _S is inputted and the horizontal frequency H _O always has a constant polarity. And a horizontal synchronous control unit 11 to make and output a polarity of the vertical synchronous signal (V _S ) to be input, and output the synchronous control unit 12 to always make and output a constant vertical frequency (V _O ); level The oscillator clock frequency (3.58) is inputted with the horizontal and vertical synchronization signals H _S (V _S ) input to the vertical synchronization controllers 11 and 12. To count and output the counted value Vertical frequency counters 13 and 14 and the horizontal Horizontal output by making duty of duty ratio according to the frequency output from vertical frequency counter 13, 14 Vertical pulse generator 15, 16, and the horizontal Horizontal and vertical controllers 17 and 18 for classifying the horizontal and vertical frequency bandwidths by the output values of the vertical frequency counters 15 and 16; Horizontal from vertical synchronous control unit (11) (12) The vertical polarity output PH and the horizontal of the horizontal and vertical controllers 17 and 18 A mode control unit 19 which detects a desired frequency band by inputting the vertical frequency bandwidth and combining the inputs, and the horizontal and vertical polarization signals PH and PV of the horizontal and vertical synchronization signals of the horizontal and vertical frequency counters 14 are horizontal. And mute pulse generator 20 to mute a predetermined time when the frequency is changed or the frequency polarity is changed by inputting the variable check output (H _T ) (V _T ) of the horizontal and vertical frequency of the vertical control unit (17) (18) ), An output selector 21 which selects a part of the input signal as an output signal according to the signal of the output mode OM input by inputting the signal output from each part, and outputs it as an output signal, and a designated external signal according to the frequency (D ₀ D ₅ ) receives the pulse width control unit 22 for outputting an address A _n and a control value C _n to the output selector 21, and oscillation according to the input oscillation signals OSC1 and OSC2. The oscillation unit 23 provides a clock CLOCK to each of the necessary units.

Referring to the operation and effects of the present invention configured as described above in detail.

First of all, referring to FIG. 2, the input negative horizontal and vertical frequencies (H _S ) (V _S ) are inverted through the inverter, and the inverted positive type horizontal and vertical synchronization are inverted. The signal H _S (V _S ) is input from the horizontal and vertical synchronous controllers 11 and 12, respectively, to determine the polarity of the frequency, and the determined polarity is determined through its polarity output terminal PH (PV). Output to the control unit 19, the mute pulse generator 20 and the output selector 21 and at the same time to make a horizontal and vertical frequency (H _O ) (V _O ) having a constant polarity at all times.

Here, the detailed operation of the horizontal synchronization controller 11 will be described later.

In this way, the horizontal and vertical frequencies are always the same polarity, so even if various horizontal and vertical frequencies are used, The deviation according to the frequency of the vertical position can be reduced.

In addition, the horizontal and vertical frequency counters 13 and 14 convert the input horizontal and vertical frequencies into the oscillator clock frequency (3.58). When the counted frequency value is provided to the horizontal and vertical pulse generators 15 and 16, the horizontal and vertical pulse generators 15 and 16 have a predetermined ratio according to the counted frequencies. The pulses FVH (FVV) having the duty DUTY are outputted to the output selector 21.

In addition, the horizontal and vertical frequency counters 13 and 14 receive the horizontal and vertical frequency counts output from the output terminals OUT of the horizontal and vertical control units 17 and 18, respectively. Are classified and provided as input terminals H and V of the mode control unit 19, respectively.

The mode control unit 19 is provided with the polarity output PH (PV) of the horizontal and vertical synchronization signals provided from the horizontal and vertical synchronization controllers 11 and 12 and from the horizontal and vertical control units 17 and 18. The horizontal and vertical frequency bandwidths are input to the input terminals H and V to detect the desired frequency band by combining the AND gate and the OR gate, and provide the detection signal to the output selector 21.

Accordingly, the output selector 21 is a mode signal M ₁ of horizontal and vertical frequencies provided from the mode control unit 19. M ₁₅ ) and an address (E ₀ ) that encodes and outputs each mode of abnormal synchronization and NO synchronization detection. E ₃ ), the horizontal and vertical frequency polarity output PH (PV) provided by the horizontal and vertical synchronous control units 11 and 12, and the horizontal and vertical pulse generators 15 and 16 provided by the horizontal unit. And the vertical frequency pulse FVH (FVV) and the address A _n and the control value Cn of the pulse width control unit 22 are input terminals A _0. A ₂ ) (C ₁ C ₆ ), respectively, selects output according to output mode (OM) and outputs M1-M5, M8-M10 and FVH, FVV, PV, PH when high (H), and output mode (OM) is low. In the state, the address A0-A2, the mode combination E0-E3, and the control signal C2-C6 are output.

At this time, the mute pulse generator 20 is horizontal Horizontal from vertical pulses (15, 16) Horizontal to the polarity output (PH) (PV) of the vertical synchronization signal Horizontal from vertical frequency counters 13 and 14 When the frequency change or the polarity change is input from the polarity change output (HT) (VT) of the vertical synchronization signal, the clock is transmitted and the mute signal is transmitted only for a predetermined period (73 ms).

The operation of each unit described above will be described in detail with reference to the accompanying drawings.

FIG. 3 is a detailed view of the horizontal synchronous control unit 11. As shown in FIG. 3, the horizontal synchronous signal H _S is received as an input terminal IN and synchronized with a clock input to the clock terminal CK. The horizontal synchronous signal polarity discrimination unit 111 for discriminating the polarity of the signal and outputting the determined polarity output PH, and the horizontal synchronous polarity signal PH determined by the horizontal synchronous signal polarity discrimination unit 111. It consists of an exclusive oar gate (XOR1) that receives each of the horizontal synchronization signal (H _S ) to output a horizontal frequency (H _O ) having a constant polarity.

The detailed diagram of the horizontal synchronizing signal polarity discriminating unit 111 is input to the data input terminal D1 for each rising edge of the horizontal synchronizing signal H _S applied to the clock terminal CK, as shown in FIG. A first deflection flop DF1 for outputting a high-level pulse for a predetermined period, an AND gate AD1 for supplying a clock until the first deflection flop DF1 is reset by the AND gate AD2; A counter 112 for counting a clock inputted through the AND gate AD1 at a predetermined frequency; and an AND gate AD4 for detecting a level of an output pulse of the counter 112 after a predetermined time elapses. A second deflip-flop DF2 for outputting a clock pulse corresponding to the output level of the AND gate AD4, and a horizontal synchronous signal H _S inputted with the output pulse of the second deflip-flop DF2 as a clock. the determination of the polarity inversion output of the third D flip-flop (DF3) and said second D flip-flop (DF2) to (P _H) Power ( ) And reset signal ( ) And AND gate AD2 (AD3) for outputting a signal for clearing with the first flip-flop DF1 and the counter 112 by AND combining.

When the horizontal synchronizing signal H _S is input to the horizontal synchronizing signal polarity discriminating unit 111 of the horizontal synchronizing control unit 11 shown in FIG. 3, the horizontal synchronizing signal polarity discriminating unit 111 is configured to generate the horizontal synchronizing signal 111. The polarity is determined and the determined horizontal synchronous polarity signal PH is outputted to the mode controller 19, the output selector 21, and the mute pulse generator 20, and the other side of the exclusive oragate XOR1. When supplied to the terminal, the one side terminal immediately receives the horizontal synchronization signal H _S and always outputs a constant polarity. Here, the negative horizontal synchronization frequency signal H _O is always output. A more detailed description will be made based on FIG. 4 below.

That is, when the horizontal synchronizing signal H _S as shown in FIG. 5 (a) is input to the clock terminal CK1 of the first flip-flop DF1, the horizontal synchronization signal H _S is not cleared by the AND gate AD2. As shown in fifth (b), the first flip-flop DF1 is connected to the data input terminal D1 through its output terminal Q1 by the data input of the high one state. A pulse having a constant width is synchronized with the rising edge of _S ) and output to the AND gate AD1. When the output pulse is high, the counter 112 sets the input clock CK as shown in FIG. 5 (c). Count by frequency.

When the counter value of the counter 112 is not equal to the input of the counter value itself, but equal to the set value after a predetermined period T, that is, when the outputs Q11-Q14 of the counter 112 are high, the AND gate AD4 is zero. The high signal is supplied to the input terminal D2 of the 2 flip-flop DF2.

Accordingly, the second flip-flop DF2 inputs a high state pulse as shown in FIG. 5 (d) to the clock terminal CK3 of the third deflip-flop DF3, and the data input terminal ( When the horizontal synchronization signal H _S as shown in Fig. 5 (a) is input to D3), the fifth deflection via the non-inverting terminal Q3 through the third flip-flop DF3 is applied. The horizontal synchronous signal H _S shown in the figure is output, and the horizontal synchronous polarity signal PH is output to the inverting terminal Q3, that is, as a signal having a polarity opposite to the horizontal synchronous signal H _S.

In addition, when outputting the negative horizontal synchronous frequency signal H _O mentioned above, the horizontal signal PH input to one side of the exclusive OA gate XOR1 is generated after a certain period of time. The signal is cleared to output a high signal, so a combination of the high horizontal sync signal becomes a negative signal. In this case, since the counter 112 is 5 counters, 2 ⁵ = 32, 32 (1 / 3.58 ) = 8.6 Later, the polarity of the desired frequency can be determined according to the increase and decrease of the discrimination counter.

The configuration of the vertical synchronous control unit 12 and its vertical synchronous signal polarity discriminating unit 12 is the same as in FIGS. 6 and 7, and its configuration and operation are the same as those of the horizontal synchronous control unit 11 mentioned above. Since the counter 122 is 12 counters in the vertical synchronous signal discrimination unit 121, 2 ¹² = 4096, 4096 (1 / 3.58 ) = 1.14 ms and determine the polarity according to the increase or decrease of the counter.

8 is a detailed circuit diagram of the horizontal frequency counter 13. As shown therein, an 8-bit counter 131 which counts 8 bits of an input clock CK in one cycle, and the 8-bit count 131 Cycle count setting unit 130 for outputting the enable and disable signals so that the controller counts once every two cycles, and first and second latch units for sequentially latching the output of the 8-bit counter 131 for a predetermined time ( 132 and 133, and the 8-bit full adder 134 that inputs the outputs of the first and second latch units 132 and 133, inverts one input, and then compares and adds the two inputs to each other. When the difference between the main clock frequency through the 8-bit full adder 134 is less than or equal to 1, the second latch unit 133 is prevented from being loaded into the second latch unit 133, and when there is a difference of 2 or more, the second latch unit 133 To the frequency change detection unit 135 for newly loading the value of the first latch unit 132 and outputting the frequency change signal HT. The Castle.

The operation of the horizontal frequency counter 13 configured as described above will be described with reference to the timing diagram shown in FIG.

When the 8-bit counter 131 counts the input clock CK as 8 bits and counts every cycle, the 8-bit counter 131 must start according to a new edge at the end of the cycle. The main clock is too short, but the flip-flop operation takes a long time. Since the counter error occurs, the seventh flip-flop DF7 outputs the pulse Q7 as shown in FIG. 9 (b) so that the one cycle count setting unit 130 counts once every two cycles.

Then, the AND gate AD8, which receives the output Q7 of the seventh flip-flop DF7 to one side, resets the reset signal to the other side thereof. ) And 8-bit counter 131 is enabled and disabled with an AND-combined pulse.

Therefore, the 8-bit counter 131 performs a counter once every two periods and outputs the counted value to be sequentially latched to the first and second latch units 132 and 133. The seventh flip-flop DF7 The first latch unit 132 having the inverted output Q7 value as a clock has an 8-bit counter 131 as shown in FIG. 9 (d) when the clock is in a high state as shown in FIG. 9 (c). ), The first latch unit 132 and the second latch unit 133 output data.

In this case, the 8-bit full adder 134 receives the output values of the first and second latch units 132 and 133 respectively input to the two input terminals A ₀ -A ₇ (B ₀ -B ₇ ), and compares them with each other. The first latch unit 132 receives the count value output from the non-inverting output terminal Q, and the second latch unit 133 receives the count value output from the inverting output terminal Q. Alternatively, the non-inverting and inverting outputs of the first latch unit 132 and the second latch unit 133 may be received.

In the above process, if there are two or more main clock frequency differences added by the 8-bit full adder 134, the non-inverting output terminal Q8 of the eighth flip-flop DF8 of the frequency change detecting unit 135 A pulse as shown in FIG. 9 (e) having a predetermined width is output through The output pulse is used as the frequency change signal HT and is supplied to the mute pulse generator 20 and input to the AND gate AD9, so that the clock CK supplied to the other side is supplied to the second latch unit 133. It is input to the clock terminal of the de-flip flop to operate the de-flop flop group to newly load the value of the first latch unit 132 into the second latch unit 133. Here, the output of the second latch unit 133 maintains the data value when the frequency does not change.

That is, the exclusive oragate (XOR3-XOR9) of the frequency change detection unit 135, which receives the comparison addition output and the rounding output of the 8-bit full adder 134, is formed of the first latch unit 132 and the first latch unit 132. When the difference between the values of the second latch unit 133 is 1 or 0, the latch signal is not applied to the second latch unit 133, and the first latch unit may be applied to the second latch unit 133 only when the difference is 2 or more. Allow the output of 132 to latch. In addition, using the exclusive Noagate instead of the Exclusive Oagate (XOR3-XOR9) in the above results the same result.

Therefore, a counter output having a different value depending on the frequency of the synchronization signal can be obtained while overcoming the error of the counter value accompanying the asynchronous signal and the clock signal.

Since the operation of the vertical frequency counter 14 is the same as the horizontal frequency counter 13, but the vertical frequency is low in frequency, the LSB 8-bit counter output is deleted from the 16-bit counter 141 shown in FIG. Only use bits.

An example of a horizontal frequency counter value for the horizontal frequency is as follows.

The counter value can be output in the same way as above. It is the value when counted by the clock, and the difference from the hexadecimal value of the third latch unit 142 by 1 is not an integer value when the horizontal frequency is divided by the clock. The output value of 143 does not change when there is no difference more than two counts compared with the output value of the third latch unit 142.

Use 8-bit counter and clock 3.58 When using, the classifiable frequency is at least (256 1 / 3.58 ) ^-1 = 13.98 Number from Since the counter can be used to increase or decrease the desired frequency. The vertical frequency is also the same, and the vertical counts by one frequency, because the frequency of the LSB 8-bit counter is lowered.

Among the output values of the horizontal frequency counter 13, when Q ₀ -Q ₆ having deleted the MSB is inputted as the data value of the horizontal pulse generator 15, the data values of Q ₁ -Q ₇ having deleted the LSB have the horizontal control unit 17 It is entered as a data value of).

As described above, the horizontal and vertical frequency counters 13 and 14 are constructed by renewing the existing method so that they can be used not only for the monitor but also for terminals and other devices.

As shown in FIG. 11, the horizontal pulse generator 15 includes an 8-bit counter 151 which counts the input 8-bit clock CK as one cycle, and an output of the 8-bit counter 151 ( Q ' ₁ -Q' ₇ ) and the count output comparison unit 152 which compares the values of the frequency counter outputs (Q ₀ -Q ₆ ) and detects only when the two values coincide with each other. A count state switching unit 153 for switching the flip-flop to a specific value according to a predetermined period, and a duty adjusting unit 154 for varying the duty according to the output of the frequency counter determined by the frequency of the synchronization signal. do.

Looking at the horizontal pulse generating unit 15 configured as described above is as follows.

The clock CK applied to the clock terminal is continuously counted by the 8-bit counter 151, and this counted value is outputted as a specific value determined through the combination of the output terminals Q ' _0- Q' ₇ . Noah gate NR1 of switching section 153 is input and outputs a pulse having a predetermined time shown in FIG. In this case, since the 8-bit counter 151 is 8 bits, 2 ⁸ = 256 is 3.58. 256 as a clock 1 / 3.58 = 71.5 μsec.

At this time, the exclusive orifices XR1-XR7 of the count output comparator 152 may output the output Q ' ₁ -Q' ₇ and the frequency counter Q ₀ -Q ₆ of the 8-bit counter 151. ) Is detected by comparison, and when the two values coincide, the ORA outputs the pulse shown in FIG. 12 (b) by the detection signal.

Then, the thirteenth flip-flop DF13 and the fourteenth flip-flop DF14 of the count state switching unit 153 use the output of the noar gate NR1 and the OR gate OR3 as data inputs. Pulses as shown in (c) and twelfth (d) are output (Q13) and (Q14).

Accordingly, the non-inverting output Q14 and the reset signal of the fourteenth flip-flop DF14 The duty is adjusted in accordance with an enable or disable state by the power supply, and the pulse FVH as shown in FIG. 12 (e) is supplied to the output selector 21.

If the data value input from the horizontal frequency counter 13 is 64 and the 0111111 is input as a binary value, the value output after passing through the 8-bit counter 151 of the horizontal pulse generator 15 is the exclusive oragate first. The pulses through (XR1-XR7) and oragate OR3 become as shown in FIG. 12 (b), which falls low when the counter value becomes 01111110 or 01111111. The pulse through the noah gate NR1 is as shown in FIG. 12 (a), which generates one pulse when the counter values are all zero.

The outputs of the thirteenth and fourteenth flip-flop DF13 and the DF14, which receive the outputs of the NOA gate NR1 and the ORG OR3 to the data input terminal, are synchronized with a clock pulse to be used to control the twelfth (c) degrees and the eighth. A pulse as shown in Fig. 12 (d) is output.

Therefore, the output of the fifteenth flip-flop DF15, which receives 1 as a data input terminal, is output by using the output of the thirteenth flip-flop DF13, which is inputted as a clock, as shown in FIG. 12 (e). A pulse having an output duty value as described above is output.

While maintaining the high state in the portion A of FIG. 12 (e), binary 0111111 (128 in decimal conversion), 128 1 / 35.8 = 35.7 The high state drops to the low state.

If horizontal frequency is 31.5 When the 8-bit counter 151 outputs the hexadecimal number 72 (binary value is 01110010), the binary value of Q ₀ -Q ₆ omitting the MSB (1110010) .The output pulse of the 11th flip-flop (DF11) is high. The length of time to keep it is 228, so 228 1 / 3.58 = 63.68 Becomes

When the waveform of the duty determined in the horizontal pulse generator 15 described above is outputted, it is possible to convert to a direct current (DC) value by double integration at the rear end.

The operation of the vertical pulse generator 16 shown in FIG. 13 is the same as the operation of the horizontal pulse generator 15 described above, except that the 8-bit counter 161 is used without deleting the LSB and MSB.

In addition, the horizontal control unit 17 shown in FIG. 14 receiving the outputs Q ₁ -Q ₇ received from the horizontal frequency counter 13 is connected to the inverters I5-I19 and AND gates AD14-AD42. In classifying and outputting the frequency values received from the ORA gates OR5-OR12 for the combined signal, the first frequency band is input (Q ₇ ) and AND gate (AD15) (AD16) from the ORA gate OR5. Value through) Oaring and outputting, and the second to seventh frequency bands are also outputted by Oaring through Fig. 14 in the same manner, the frequency band according to the frequency range can be obtained as in the example shown below.

The count is a value output from the horizontal frequency counter 13 as a decimal number and is a value of Q-Q, and the input of the horizontal control unit 17 omits Q, which is an LSB.

Therefore, it is possible to subdivide up to several tens of bands by changing the combination.

The vertical control unit 18 is the same as the principle of the horizontal control unit 17, and the configuration divided into 6 bands in FIG. 15 is shown. The frequency band, the classification value and the counter range are shown in FIG. Same as in the chart.

As shown in FIG. 16, the mute pulse generator 20 receives the horizontal and vertical synchronous polarity signals PH (PV) and the variation check signal H and V of the horizontal and vertical synchronous frequencies, respectively. The horizontal and vertical synchronous pulse change detection unit 201 which detects changes in the horizontal and vertical synchronous pulses, and when there is at least one change signal from the detection unit 201, generates a screen mute signal (MUTE) to display the state of the screen. And a counting unit 203 for counting when a mute signal MUTE is generated from the state adjusting unit 202 and returning to a previous state when a specific value is reached. do.

The circuit constructed as described above is as follows.

The vertical synchronous polarity signal PV and the horizontal and vertical synchronous frequency fluctuation check signals H and V are not changed, and the horizontal synchronous polarity signal PH output from the horizontal synchronous control unit 11 is the 17th (a). As shown in the figure, when there is a characteristic change, the output Q19 of the nineteenth flip-flop DF19 of the horizontal / vertical synchronous pulse change detection unit 201 is in a high state as shown in Fig. 17 (c). Output a pulse. At this time, the 20th flip-flop DF20 has no variation in the vertical synchronous polarity signal PV, so that the exclusive oar gate XR20 outputs a clock pulse as shown in FIG. 17 (d).

Therefore, the high-level pulse is transmitted through the deflip-flop DF19 (DF20), the exclusive oragate (XR19), the XR20, and the oragate OR16. When outputting to the clock terminal of (), the 21st flip-flop (DF21) outputs a mute signal (MUTE) having a predetermined period before the clear state by the AND gate AD60 to its output terminal (Q21).

At this time, the 4-bit counter 204 and the 16-bit counter 205, which receive the mute signal MUTE of the state control unit 202 through the AND gate AD61, respectively perform counters and then the 4-bit counter 204. When the counter value Q3 reaches a predetermined value, the twenty-first deflip-flop DF21 is reset via the inverter 127 as a signal as shown in FIG. 17 (g), and the mute signal is no longer output. Do not do it.

As shown in FIG. 18, the mode control unit 19 includes the horizontal frequency HH from the horizontal control unit 17, the vertical frequency VV from the vertical control unit 18, and the horizontal and vertical synchronous control unit 11. A horizontal and vertical synchronous signal (PH) (PV) is inputted from (12), and a desired function is generated by combining the inverters, the gates of the AND gates, and the OR gates. The present invention generates and outputs a total of 16 modes. .

As an example of the present invention, a total of 16 modes have a horizontal frequency of 31 -78 Vertical frequency 56 -87 15 modes up to and including one mode for SYNC or asynchronous detection and addresses E0-E3 that encode and output each mode, and mode detection (M1-M9) are arbitrarily combined by gate combination. It is possible.

In general, VGA mode is classified into three types according to resolution. When classified into modes 1, 2, and 3,

Mode 1 has a resolution of 640 350 31.5 70 PH + PV-

Mode 2 has a resolution of 640 400 31.5 70 PH- PV +

Mode 3 has a resolution of 640 480 31.5 60 It is PH- PV- and Modes 1, 2, and 3 are distinguished as H1 (output value of horizontal frequency control) PH and PV, and they are denoted as M1 (A), M2 (B), and M3 (C), respectively. , 86.96 As H2 and V1, it is expressed as M4 (D).

By the same principle as above, it is divided into 16 parts and the encoding output E0-E3 is classified by FIG.

That is, for example, the value of E0-E3 in the case of mode 1 (M1) is 0000, and the value of E0-E3 in the case of mode 5 (M5) is 0010.

The mode control table table for this is shown in FIG. 20, and the address combination table table is shown in FIG.

The output of the mode shown in FIG. 18 is obtained as follows.

E0 = E2 + M4 + M6 + M8 + M10 + M12 + M14 + M16

E1 = M3 + M4 + M7 + M8 + M11 + M12 + M15 + M16

E2 = M5 + M6 + M7 + M8 + M13 + M14 + M15 + M16

E3 = M9 + M10 + M11 + M12 + M13 + M14 + M15 + M16

E0 = B + D + F + H + J + L + N + (P + Q)

E1 = C + D + G + H + K + L + O + (P + Q)

E2 = E + F + G + H + M + N + O + (P + Q)

E3 = I + J + K + L + M + N + O + (P + Q)

FIG. 22 is a circuit diagram of the pulse width control unit 22. As shown therein, an address generator 222 receives a specified external signal according to frequency and outputs corresponding addresses A ₀ -A ₂ . And a clock generator 223 for generating a clock pulse by logically combining external data and a counter output according to the frequency, a demultiplexer 224 for selecting an output by changing an address according to the output of the clock generator 223; The pulse width adjusting unit 225 adjusts the pulse width by the input output from the demultiplexer 224 according to the input clock. In this case, the pulse width adjusting unit 225 includes only the flip-flops DF23-DF34 and the end gates 62-67.

Referring to the circuit configured as described above, the counted clock CK of the 9-bit counter 221 of the address generator 222 outputs the counted value in one cycle of 9 bits. When the counter value of 221 and the external data (D ₀ -D ₅ ) are the same, the state falls from high to low. Therefore, the noah gate NR4 is 143 as shown in FIG. 24 (a). It outputs a low signal with a period because the counter 221 is 9 bits, so the total period is 2 ⁹ = 512, 512 1 / 3.58 = 143 To be.

Then, the 22nd flip-flop DF22 outputs the same pulse as that of the noble gate NR4 as shown in FIG. 24 (b).

At this time, counting in the 9-bit counter 221 counts by 9 bits as shown in FIG. 24 (c).

When the data (D ₀ -D ₅ ) inputted from the outside and the output of the 9-bit counter 221 are the same, the NOA gate NR5 maintains 8 clocks as shown in FIG. 24 (d) to demultiplexer. Output to (224).

The pulse width control unit 225 changes the output of the clock pulse input from the NOR gate NR5 according to the address A ₀ -A ₂ input from the 9-bit counter 221 by the demultiplexer 224. When the data is input to the def flip-flop, the control values C1 to C6 are changed as shown in FIGS. 24 (e) to (i).

An example of this is as follows.

If the value of external data (D ₀ -D ₅ ) is set as below,

The pulse width is adjusted and output to the output selector 21 according to the timing diagram as shown in FIG.

Therefore, the output selector 21 finally selects and outputs the signals P1-P13 which are input by the input output mode OM. The configuration diagram of the two inverters and the end is shown in FIG. It consists of a gate and an oar gate.

When the output mode OM is in a high state, it is output through the output controller 21 as follows.

P1 = M1 VGA1, P2 = M2 VGA2, P3 = M3 VGA3, P4 = M4 8515 / i

P5 = M5 EVGA1, P6 = M8 VESA, P7 = M9 EVGA2, P9 = M10 8514 / Ni

P10 = output of the FVV vertical pulse generator 16,

P11 = PV vertical pulse polarity,

P12 = output of the FVH horizontal pulse generator 15,

P13 = PH horizontal pulse polarity,

In addition, when the output mode OM is low, the output of the output selector 21 is

P1 = A0, P2 = A1, P3 = A3, P4 = E0, P5 = E1, P6 = E2, P7 = E3

P9 = C2 Use the vertical size compensation as the value output from the pulse width control section 22,

P10 = C3 Horizontal size compensation

P11 = C4 Vertical center (CENT) compensation,

P12 = C5 Using horizontal position compensation,

P13 = C6 Each is used for side pincushion compensation.

The output selector 21 outputs the mode (M ₁ -M ₁₅ ) output and address (E ₀ -E ₃ ), horizontal and vertical synchronous control unit (M ₁ -M ₁₅ ) input from the mode controller 19 according to the output mode (OM) signal. 11) Horizontal and vertical synchronous signal PH (PV) output from (12) and horizontal and vertical frequency change output (FVH) (FVV) generated from horizontal and vertical pulse generators 15 and 16. Any one of them is selected and outputted, but the address A ₀ -A ₂ and the control output C ₁ -C ₆ outputted from the pulse width control unit 22 are not necessarily required.

As described in detail above, the present invention can -Number Frequency band up to can be detected and the range of output can be extended by selecting more than 16 different outputs by selecting the output mode of output mode, and this circuit method is converted into ASIC to reduce cost and space. It can automatically select different sync signal from monitor or terminal, and the change according to frequency is automatically set and then corrected, which greatly reduces the number of parts, making it very effective for improving productivity.

Claims (18)

The horizontal synchronous control unit 11 and the vertical synchronous signal V _S input to discriminate and output the polarity of the input horizontal synchronous signal H _S and to make and output the horizontal frequency H _O having a constant polarity at all times. also of determining and outputting a polarity as well as always constant vertical frequency (V _O) to create an output vertical synchronizing control section 12 and the horizontal and vertical and horizontal synchronization signal input to the vertical sync controller 11 (12) in ( H _S) (V _S) for receiving the oscillator clock frequency (3.58 ) And a duty ratio of a constant ratio depending on the frequency output from the horizontal and vertical frequency counters 13 and 14, which counts the output and outputs the counted value. Horizontal and vertical pulse generators 15 and 16 for outputting and outputting the horizontal and vertical frequency bandwidths by the output values of the horizontal and vertical frequency counters 15 and 16. And horizontal and vertical frequency bandwidths of the horizontal and vertical polarity outputs (PV) from the horizontal and vertical synchronous control units 11 and 12 and the horizontal and vertical frequency bandwidths of the horizontal and vertical control units 17 and 18 as inputs. A mode control unit 19 for detecting a desired frequency band by combining inputs thereof, a polarity output PH (PV) of horizontal and vertical synchronization signals of the horizontal and vertical frequency counters 14, and a horizontal and vertical control unit 17 ( 18 checks the variation of the horizontal and vertical frequencies), the output (H _T) (V _T) to the input frequency is changed, or the frequency Mute pulse generator 20 to mute a predetermined time when the polarity changes, and selects some of the input signal according to the output mode (OM) signal inputted by the signal output from each part to output as an output signal An output selector 21 and a designated external signal D ₀ according to frequency. D ₅ ) receives the pulse width control unit 22 for outputting an address A _n and a control value C _n to the output selector 21, and oscillation according to the input oscillation signals OSC1 and OSC2. A frequency discrimination and compensation circuit of a monitor, comprising: an oscillator (23) for providing a clock (CLOCK) to each required part. The horizontal synchronous control unit 11 receives the input horizontal synchronous signal H _S as an input terminal IN and determines the polarity of the signal by synchronizing with a clock inputted to the clock terminal CK. The horizontal synchronous signal polarity judging unit 111 for outputting the discriminated polarity output PH, the horizontal synchronous polarity signal P _H determined by the horizontal synchronous signal polarity judging unit 111, and the horizontal synchronous signal H _S inputted. ) A frequency discrimination and compensation circuit of a monitor, characterized in that it consists of an exclusive oragate (XOR1) that receives each input and outputs a horizontal frequency (H _O ) with a constant polarity at all times. 3. The method of claim 2, wherein the horizontal synchronizing signal polarity discriminating unit 111 supplies a high state pulse input to the data input terminal D1 for a predetermined period every rising edge of the horizontal synchronizing signal H _S applied to the clock terminal. A first flip-flop DF1, an AND gate AD1 for outputting a clock until the first flip-flop DF1 is reset by the AND gate AD2, and input through the AND gate AD1. A counter 112 for counting a clock at a predetermined frequency, an AND gate AD4 for detecting a level of an output pulse of the counter 112 after a predetermined time elapses, and a clock corresponding to the output level of the AND gate AD4 The second deflip-flop DF2 for outputting a pulse and the output pulse of the second deflip-flop DF2 as clocks are used to discriminate the polarity of the input horizontal synchronization signal H _S and output the output P _H. The third flip-flop DF3, the inverted output of the second flip-flop DF2, and the reset signal RESET are applied. And an AND gate (AD2) (AD3) for outputting a signal for clearing with the first flip-flop (DF1) and the counter (112) by combining. The frequency discrimination and compensation circuit of a monitor according to claim 1, wherein the vertical synchronization controller (12) has the same principle and configuration as the horizontal synchronization controller (11). The method of claim 1, wherein the output selector 21 receives the specified external signal according to the frequency, and when the pulse width control unit 22 is further configured to adjust the pulse width, its address and control value are also received and selectable. Frequency discrimination and compensation circuit of monitor. 2. The address generator 222 of claim 1, wherein the pulse width controller 22 receives an external signal designated according to a frequency and outputs an address A ₀ -A ₂ corresponding to the frequency, and the address generator 222. A clock generator 223 for generating a clock pulse obtained by logically combining exclusive data based on the count value and the frequency generated by the external or gate and the address according to the output of the clock generator 223. The demultiplexer 224 selects an output by changing an address input from the generator 222, and the pulse width adjuster 225 adjusts a pulse width by an input output from the demultiplexer 224 according to a clock. Frequency discrimination and compensation circuit of the monitor, characterized in that configured. The horizontal frequency counter 13 is an 8-bit counter 131 that counts 8 bits of an input clock CK as one cycle, and the 8-bit counter 131 counts once every two cycles. 1 cycle count setting unit 130 for outputting an enable and disable signal, first and second latch units 132 and 133 for sequentially latching an output of the 8-bit counter 131 for a predetermined time; An 8-bit full adder 134 for inputting the outputs of the first and second latch units 132 and 133, inverting one of the inputs, receiving the inputs, and comparing and adding the two inputs to each other, and the 8-bit full adder. If the difference between the main clock frequency through the 134 is less than or equal to 1, the second latch unit 133 is prevented from being loaded, and when there is a difference of 2 or more, the first latch unit 132 is connected to the second latch unit 133. The frequency change detection unit 135 for newly loading (loading) the value and outputting the frequency change signal HT. Frequency discrimination and compensation circuit. 8. The seventh flip-flop DF7 according to claim 7, wherein the one cycle count setting unit 130 adjusts and outputs the pulse width of the input applied to the data input terminal using the input synchronization signal as a clock. Non-inverted output and reset signal of the flip-flop (DF7) Frequency discrimination and compensating circuit of the monitor, characterized in that the eighth gate (AD8) to configure the counter to counter once every two cycles. The frequency change detection unit (135) of claim 7, wherein the frequency change detection unit (135) outputs a seven-bit output of the eight-bit full adder (134) and a carry out output of the eight-bit full adder (134) through the inverter (I3). 7 exclusive oragates (XOR3-XOR9) for receiving the difference value, an oragate (OR1) for adding the output of the exclusive oragate (XOR3-XOR9), and the oragate according to the clock. A second latch by supplying and blocking a clock according to the output of the eighth flip-flop DF8 for outputting a pulse having a predetermined width using the output of OR1 as a data input; A frequency discrimination and compensation circuit of a monitor, characterized in that it comprises an end gate (AD9) for adjusting the hold state of the unit (132). The method of claim 7, wherein the exclusive orifice (XOR3-XOR9) is the second latch portion 133 when the difference between the output value of the first latch portion 132 and the second latch portion 133 is 1 or 0. And a latch signal is not applied to the second latch unit, and the output of the first latch unit 132 is latched to the second latch unit 133 only when the latch signal is 2 or more. The horizontal pulse generator (15) according to claim 1, wherein the horizontal pulse generator (15) includes an eight-bit counter (151) for counting the input eight-bit clock (CK) in one cycle, and the output (Q ' _1- ) of the eight-bit counter (151). Q ' ₆ ) is compared with the value of the frequency counter output (Q ₀ -Q ₆ ), and the count output comparison unit 152 detects only when the two values match, and the counter value of the 8-bit counter 151 is constant. The count state switching unit 153 for switching to a specific value of the flip-flop in accordance with the period and the duty adjustment unit 154 to vary the duty according to the output of the frequency counter determined by the frequency of the synchronization signal Frequency discrimination and compensation circuit of monitor. 12. The count output comparison unit 152 receives an output of a frequency counter and an output of an 8-bit counter 151 that counts a clock, and receives the output of the frequency counter. Frequency discrimination and compensation circuit of the monitor, characterized in that configured. The count state switching unit 153 combines each bit of the output of the 8-bit counter 151 and outputs the arrival state when the counter reaches a predetermined value. The OR gate OR3 for detecting the output state by combining each bit of the output of the count output comparison unit 152, and the outputs of the NOA gate NR1 and the OR gate OR3 are respectively input to the data input terminal to the clock. And a thirteenth and fourteenth flip-flop (DF13) (DF14) for outputting the pulse width by adjusting the pulse width. 12. The AND gate AD12 of claim 11, wherein the duty cycle controller 154 combines the output of the fourteenth flip-flop DF14 and the reset signal to generate and output an enable signal and a disable signal. And a fifteenth flip-flop (DF15) for adjusting the duty by determining the pulse width according to the output of the gate AD12. The mute pulse generator 20 receives the horizontal and vertical synchronous polarity signals PH and the change check signal H _T and V _T of the horizontal and vertical synchronous frequencies, respectively. Horizontal and vertical synchronous pulse change detection unit 201 for detecting a change in the vertical synchronous pulse, and the state control unit for generating a screen mute signal when there is at least one change signal from the detection unit 201 to adjust the state of the screen And a counting unit (203) which counts from when the mute signal is generated from the state adjusting unit (202) and returns to the previous state when a specific value is reached. 16. The apparatus of claim 15, wherein the horizontal / vertical synchronous pulse change detection unit 201 detects a change in the horizontal / vertical synchronous polarity signal P _H (P _V ) input to the data input terminal in synchronization with a clock. The deflip-flop DF19 (DF20), the outputs of the 19th and 20th flip-flop DF19 (DF20), and the horizontal and vertical synchronous signal PH (PV) are respectively input to detect a change signal. Input the exclusive oragate (XR19) (XR20), the output signal of the exclusive oragate (XR19) (XR20), and the variable check signal (H _T ) (V _T ) of the horizontal and vertical synchronization frequencies, respectively. A frequency discrimination and compensation circuit of a monitor, characterized in that it comprises an oragate (OR16) for receiving and outputting the signal to the signal. The twenty-first flip-flop DF21 according to claim 15, wherein the state controller 202 adjusts the screen mute time according to the change detection output of the horizontal / vertical synchronous pulse change detection unit 201 and outputs a screen mute signal. And an AND gate AD60 for controlling the mute time of the twenty-first flip-flop DF21 according to the counter output of the 4-bit counter 205 through the inverter I27. And compensation circuitry. A first step of detecting and counting rising edge sections of the synchronization signal; and a second step of starting counting when the rising edge section is detected in the first step and detecting the level of the counted clock pulse after a predetermined time (T) has elapsed. And in the second step, if the level is high, the clock frequency is determined to be negative and outputs a low signal. If the level is low, the clock frequency is determined to be positive and outputs a high signal. How to determine the frequency of the monitor.