JPH01230094A - Deciding circuit for video signal - Google Patents

Abstract

PURPOSE:To accurately decide a video signal even when the period of a horizontally synchronizing signal of a video signal is unstable by deciding whether the video signal is interlaced or not in accordance with output values from the 1st and 2nd latch circuits, and when the video signal is interlaced, deciding whether the signal is included in an even or odd field. CONSTITUTION:An output signal from a PLL circuit 15 for inputting a horizontally synchronizing signal HSY of an average period 1H in a video signal to one input is divided into N frequency levels and its frequency divided signal hSY is inputted to the other input of the PLL circuit 15. A count value C of an N-frequency division counter 16 is latched synchronously with a vertically synchronizing signal VSY of the video signal, and a holding value Y of the 1st latch circuit 17 is latched synchronously with the vertically synchronizing signal VSY. Whether the video signal is interlaced or not is decided by respective held values Y, X of the 1st and 2nd latch circuits 17, 18, and when the video signal is interlaced, which field out of the even and odd fields includes the video signal are decided. Even when the period of the horizontally synchronizing signal is changed, the video signal can be accurately decided.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention is an interlaced video signal suitable for use in, for example, a scan converter device in which video signals of various formats are viewed on the same monitor. The present invention relates to a video signal discrimination circuit for discriminating whether the field is an even number field or an odd number field when the field is interlaced.

[Essentials of invention]

The present invention is suitable for use in, for example, a scan converter device in which video signals of various formats are viewed on the same monitor. This is a video signal discrimination circuit for determining which field the video signal belongs to, and includes a PLL circuit that takes the horizontal synchronization signal of the video signal as one input, and a frequency division circuit that divides the output of this PLL circuit. A counter that receives a signal as the other input of its PLL1 path, a first latch circuit that latches the counted value of the counter in synchronization with the vertical synchronization signal of the video signal, and a first latch circuit that synchronizes with the vertical synchronization signal of the video signal. and a second latch circuit that latches the held value of the latch circuit, and the output values of the first and second latch circuits determine whether the video signal is interlaced or not, and if it is interlaced, it is determined whether the video signal is even or odd. By determining which field it belongs to, accurate determination can be made even if the period of the horizontal synchronizing signal of the video signal is unstable.

[Conventional technology]

Video signals generally used an interlaced system, as typified by television. However, in recent years, many personal computers, etc., which have become popular at m-speed, output video signals in a non-interlaced manner. Therefore, an image processing system that stores these video signals in, for example, a frame memory and performs a predetermined calculation on each pixel, or converts various input video signals with various horizontal frequencies into video signals with a predetermined horizontal frequency. In scan converter devices, etc. that output video signals to a common monitor, there is a circuit that determines whether the input video signal is interlaced or non-interlaced, and if it is interlaced, whether it is an even or odd field. It has become necessary.

Conventionally, a circuit as shown in FIG. 4 has been proposed as a video signal discrimination circuit used for such applications. In FIG. 4, +1) is an input terminal to which a video signal as a composite video signal is input. This video signal is input to the synchronization separation circuit (2), and the horizontal synchronization signal Hs
V and a vertical synchronization signal VSV are separated, and the horizontal synchronization signal Hsy is a phase-locked loop (hereinafter referred to as PLL).
) is supplied to one input terminal (3a) of the circuit (3). The average pulse interval of this horizontal synchronization signal Hsy is one day, and H means the average horizontal period. The output terminal (3c) of the PLL circuit (3) is connected to the other input terminal (3b).
), and the PLL circuit (3) has the function of changing its output so that the rising phases of the input signals to its two input terminals (3a) and (3b) are equal. Horizontal synchronization signal Hs from terminal (3c)
The frequency and rising phase are equal to v, and the duty ratio is 5.
A 0% signal HGY' is output. This signal HSY
' is supplied to the latch circuit vlrf41, and since the vertical synchronizing signal VSY is supplied to the trigger terminal of the latch circuit (4), the vertical synchronizing signal V is supplied to the latch circuit (4).
The level of the signal HGY' is held at the rising edge of SY. Then, the output signal 0/E of the latch circuit (4) is supplied to another latch circuit (5), and the trigger terminal of the latch circuit (5) Since the vertical synchronizing signal I3Y is also supplied to the latch circuit (5) at the rising edge of the vertical synchronizing signal VSY,
The output signal of the latch circuit (4) is held. The output signals of these two latch circuits (4) and (5) are input to an exclusive OR gate (6);
The output 1/N of 6) becomes high level "1" when the input video signal is interlaced, and becomes low level "0" when it is non-interlaced. Further, the output signal 0/E of the latch circuit (4) is set to a high level when the input video signal is interlaced and an even field, and to a low level when the input video signal is an odd field.
These output signals (hereinafter referred to as discrimination signals) 0/E and I
/N are output from terminals (7) and (8) to subsequent circuits, respectively.

Conventionally, a discrimination circuit as shown in FIG. 6, which is an analog version of the circuit shown in FIG. 4, has also been used. In FIG. 6, the parts corresponding to the circuit in FIG. 4 are given the same reference numerals and their explanations are omitted, but basically the circuit in FIG. 4)) L L circuit (
3) and the latch circuit (4) are replaced by a sawtooth wave generation circuit (9).
), a sample hold (S/H) circuit (lO), and a comparator (11). The output F of the sawtooth wave generation circuit (9) is a sawtooth wave with an average period of IH and a maximum amplitude voltage of Vl)I), and the comparator (
The reference voltage input terminal 11) is connected to a DC power supply (lla) with a voltage of V pp/2.

[Problem to be solved by the invention]

However, in such conventional discrimination circuits, especially when the period of the horizontal synchronization signal Hsy fluctuates greatly, such as when the input video signal is a playback signal of a cassette-type VTR or an output signal from a computer, There was an inconvenience that there was a risk of malfunction.

For example, in the discrimination circuit shown in FIG. 4, the video signal is non-interlaced, and the horizontal synchronizing signal HGY is a regular signal (2a) in which one cycle is exactly IH as shown in FIG. 518.
Consider the case where there is a deviation from First, the vertical synchronization signal V sv
At the first and second rising time points L1 and t2 (FIG. 5C), the signal HSY' (FIG. 5B) is at a low level, and the output signal 1/N of the exclusive OR gate H61 is also at a low level. Therefore, the discrimination circuit is operating normally. However,
Third rising time t3 of vertical synchronization signal VSY (fifth
In Figure C), since the horizontal synchronizing signal HsY and signal Hsv' are deviated (Figure 5 A and B), the output of the latch circuit (4) becomes high level, and the exclusive OR gate (6) determines JJ (R+ I/N changes to high level (
FIG. 5D) The input video signal is determined to be interlaced. Similarly, even when the high-power video signal is interlaced, the levels of the discrimination signals I/N and O/E change from their original values due to slight jitter in the horizontal synchronization signal HGY, causing the discrimination circuit to malfunction. There was an inconvenience.

Especially when moving from an even field to an odd field in a non-interlaced signal or an interlaced signal,
If the time difference Δt between the rises of the horizontal synchronization signal H13Y and the vertical synchronization signal Vsy (Fig. 5C) is inherently small, depending on the circuit, the time difference Δt may be almost 0, resulting in very slight horizontal synchronization. There is a problem in that fluctuations in the period of the signal HGY cause malfunction of the discrimination circuit.

Further, the conventional discriminating circuit shown in FIG. 6, which is simply an analog version of the circuit shown in FIG. 4, has similar problems.

JP-A-60-171870 and Japanese Patent Application No. 1983-
No. 270,727 discloses a circuit that determines whether the field is odd or even, but does not determine whether the video signal is interlaced or not.

The present invention has been made with consideration to the above points, and its object is to provide a video signal discrimination circuit that does not malfunction even if the period of the horizontal synchronizing signal varies.

[Means for Solving the Problems] A video signal discrimination circuit according to the present invention, for example, as shown in FIG.
A PLL circuit (15) with one input as
A divide-by-N counter (16) divides the output signal of the circuit (15) by N (N is a natural number) and inputs the divided signal hsv to the other input of the PLL circuit (15), and vertical synchronization of the video signal. The N frequency division counter (16
), and a second latch circuit (17) that latches the held value Y of the first latch circuit (17) in synchronization with the vertical synchronization signal V OY. 18), and its first and second latch circuits (
The values Y and X held in 17) and (18) are used to determine whether the video signal is interlaced or not, and if it is interlaced, whether it is an even or odd field. be.

[Effect]

According to the present invention, the phase of the horizontal synchronizing signal Hsv at the rising edge of the vertical synchronizing signal VSY is determined by the latch circuit (1
7) is specified as the holding value Y with a resolution of 360°/N. Furthermore, the held value Y of this latch circuit (17) is changed to the held value X of the latch circuit (I8) at the next rising edge of the vertical synchronizing signal VGY.
Therefore, the phase of the horizontal synchronizing signal VSY at the rising edge of the vertical synchronizing signal Hsy one cycle before is determined as the holding value X with a resolution of 360°/N. Therefore, 360
'l If the value of X-Y l /N is between 90° and 270°, the video signal can be determined to be interlaced,
If the value of 0°Y/N is between 90° and 270°, it can be determined that the subsequent video signal is in an even field.

〔Example〕

Hereinafter, one embodiment of the video signal discrimination circuit of the present invention will be described with reference to the drawings.

Figure 1 shows the video signal discrimination circuit of the actual 1111 example.
(13) and (14) indicate input terminals, the negative input terminal (13) is supplied with a horizontal synchronizing signal HsY with an average period IH separated from the composite video signal, and the other input terminal (14) ) is supplied with a vertical synchronizing signal VSY≠ separated from the composite video signal. Furthermore, horizontal synchronization signal H
3Y is one input terminal (15a) of the PLL circuit (15)
is input to the output terminal (15c) of the PLL circuit (15).
is connected to the counting terminal of the N frequency division counter (16). In this example, it is set to N - 256, and an 8-bit binary counter is used as the N frequency division counter, and the maximum digit of the count value C is The inverted output terminal (16a) of the PLL circuit (
15) is connected to the other input terminal (15b).

As shown in Japanese Patent Application No. 61-270727, the PLL circuit consists of a phase comparator circuit, a low-pass filter, and a voltage-controlled oscillator, and is configured so that the phases of two input signals to the phase comparator circuit are equal. This circuit adjusts the frequency and phase of the output signal. Therefore, PLL circuit (15)
The output signal P of the PLL circuit (15) is set so that the frequencies and phases of the two input signals HGY and hsy are equal to each other.
Since sv is determined, the frequency of the output signal PAY is N times the frequency fH of the horizontal synchronizing signal HSY, and the output signal PSY includes N pulses during the period IH. In addition, the N frequency division counter (16) integrates the output signal PSY, and when the value reaches N, the count value C returns to O, so the count value C divides the phase of the horizontal synchronization signal HSY by an IW function of 360°/
You can think of it as being displayed as N.

In FIG. 1, (I9) indicates a D-type flip-flop. The data terminal of this flip-flop (19) receives the vertical synchronizing signal VSY, and the clock terminal receives the output signal P3Y of the PLL circuit (15). However, since the signal PGY is a high-frequency signal, the vertical synchronization signal VGY is input to a flip-flop (
19) may be output as is from the output terminal.

Next, the d count value C of the N frequency division counter (16) is latched by the latch circuit (17) at the timing of the rise of the blade signal of the flip-flop (19), and the latch circuit (17)
The count value C at the time of latching is held as the value Y in the output of the latched value. In addition, the output value Y of the latch circuit (17) is input to the latch circuit (18), which also has a flip-flop (
The value of Y at the time of latching is held as the output value X in the latch circuit (18). Furthermore, the latch circuit (17
) is supplied to the comparison circuits (20) and (21), and the output value X of the latch circuit (18) is supplied to the comparison circuit (20).
is supplied to

Here, the comparison circuit (20) determines that when the absolute value of the phase difference of the horizontal synchronizing signal HsY at the rising edge of the vertical synchronizing signal VGy at one cycle interval is between 90° and 270°, the video signal is interlaced. When the input values X and Y are 90°<360°I X-Y I/N<270°, That is, N/4 < l X-Y l < 3N/4...
・(When it is 11, the discrimination signal 1/N of the comparison circuit (20)
is at a high level, and when the input values X and Y do not satisfy equation (1), the discrimination signal 1/N is at a low level.
The phase of the horizontal synchronizing signal H3Y at the rising edge of Y is 90
270 degrees, the subsequent video signal is determined to be an even field, and the output signal 0/E is kept at a high level "0". This means that when the input value Y is 90° <360" Y/N < 270°, that is, N/4 < Y < 3N/4 (2), the When the discrimination signal 0/E becomes high level and the input value Y does not satisfy equation (2), the discrimination signal 0/E becomes low level, indicating that the subsequent video signal is an odd field. Discrimination signal 1/ output from both comparison circuits (2o) and (21)
N and 0/E are output terminals (22) and (23) respectively
from which it is output to subsequent processing circuits.

Next, to explain the operation of the discrimination circuit of this example when the input video signal is non-interlaced, in the case of non-interlaced, the horizontal synchronization signal Hsv separated from the video signal is
and vertical synchronization signal V3Y are as shown in Figure 2 A and B.
The phase relationship of the rising edge is always set to be substantially constant.

First, the rising time t-t4 (second
In Figure B), the phase of the horizontal synchronization signal H8Y is the count value Y
o is held in the latch circuit (17), and the output value Y (assuming = Yo) of the latch circuit (17) at that time is held in the latch circuit (18), so it is 1, and the comparison circuit (20)
The values of the signal values X and Y inputted to are both Yo. Here, the time difference Δt between the rises of the horizontal synchronizing signal Ht3Y and the vertical synchronizing signal V3Y (Fig. 2B) is
Since it is set so that Δt << I H for one period IH of Y, Yo=N
...(3) holds true. In this case, x-y-
o, and the discrimination signal 1/ which is the output of the comparator circuit (20)
N becomes low level (Fig. 2 E), and the discrimination circuit is operating normally. Similarly, at the rising time ts of the vertical synchronizing signal Vsy (FIG. 2B), the signal values X and Y both become Yo, so the discrimination signal 1/N remains at the low level.

Next, the rising time tc (second
In Figure B), the horizontal synchronizing signal HGY is a regular signal (1
3a) as shown in FIG. 2A, the value Y1 is latched in the latch circuit (17), and this value becomes the output value Y. Here, from the assumption, Y1~0
...(4) holds true. In this case, since the value Yo is held in the latch circuit (18), the output value X becomes YO, but from equations (3) and (4), l X-Y I = l YOYL I ~N holds true, Since the condition of equation (1) is not satisfied, the comparator circuit (2
The discrimination signal 1/N, which is the output signal of 0), remains at a low level as shown in Figure 2E, indicating that the circuit of this example does not malfunction even if there is a fluctuation in the period of the horizontal synchronizing signal HSY. .

Next, to explain the operation of the discrimination circuit of this example when the input video signal is interlaced, in the case of interlaced, the horizontal synchronizing signal HGY and vertical synchronizing signal Vsv are as shown in FIG.
As shown in FIGS. and B, the phase relationship of the rising edges is almost in phase just before entering the odd field, but is out of phase by approximately 180° just before entering the even field.

First, at the rising time 1=11 of the vertical synchronizing signal Vsv (FIG. 3B), the phase of the horizontal synchronizing signal H3Y reaches the count value Yo.
is held in the latch circuit (17) as the output value, and the immediately preceding value Y2 (assumed to be ~N/2) is held as the output value X of the latch circuit (18) (Fig. 3D).
Therefore, from equation (3), l X-Y l = l Yl
-Yo1~N/2 is established, and the discrimination signal 1/N as the output signal of the comparator circuit (20) becomes high level as shown in the 31st page, indicating that the input video signal is interlaced. Next, the rising time ts of the vertical synchronization signal VSY
In (Fig. 3B), the phase of the horizontal synchronizing signal HGY is approximately 180°, and the count value Y2 (~N/2) becomes the output value Y of the latch circuit (17), and the output of the latch circuit (18). The value of the value X becomes Yo, which is the value of Y immediately before it (the third
Figure D). Therefore, IX Yl-IYOYl l''N/2 is established, and the discrimination signal 1/N remains at high level.Similarly, at the rising time t9 (FIG. 3B) of the vertical synchronizing signal VSY,
The values of X and Y are simply Yl and Yo, respectively, and the discrimination signal 1/N from the comparator circuit (20) remains at a high level.

Here, the rising time t10(
In the vicinity of Fig. 3B), the horizontal synchronization signal H5Y is a normal signal (
13a') to ±α(
Assuming that the periodic variation fluctuates (±αH/N), the count value C equivalent to the phase of the horizontal synchronization signal HSY at the rising time t10 of the signal VSY becomes Y3. ) can be expressed as This Y3 becomes the output value Y of the latch circuit (17), and the value of Y immediately before that, Yo, is the output value Y of the latch circuit (18).
The output value is X, so Yo=N-1, Yl -N/
2 1, then from equation (5), l X Y 1. −
l YOY3 l = N/ 2 YOY α ・・・(6)
holds true. Therefore, if the phase fluctuation of the horizontal synchronization signal HAY is smaller than ±90°, 0≦α<N/4 holds, so from equation (6), N/4< l X−Y l <3N/4 is satisfied. Therefore, the discrimination signal 1/N from the comparator circuit (20) maintains a high level.

Furthermore, the even/odd field discrimination signal τ/E is at a high level only when the output value Y (Fig. 3D) of the latch circuit (17) at each rising point of the vertical synchronizing signal V GY satisfies equation (2). Therefore, as shown in FIG. 3F, the vertical synchronization signal V
At the rising edge of 3Y, t8 and tto, the signal changes to the /'% level, correctly indicating that the subsequent field is an even field. In particular, at the rising time t to of the vertical synchronization information @fV 3Y, the output value Y becomes Y3 (~N/2±α) due to the periodic fluctuation of the horizontal synchronization signal Hsv, but if the periodic fluctuation is within ±90°, it is approximately equal to (2) is satisfied, so
Even-odd field discrimination signal 'i) O/E maintains high level.

As described above, according to the discrimination circuit of this example, the horizontal synchronization signal HGY
If the period variation J is within ±90'', there is an advantage that the discrimination signals 1/N and O/E can be generated without malfunction.

In addition, in the discriminator circuit of this example, the comparison circuit (20) is based on equation (1).
Although the video signal is determined to be interlaced when the following is satisfied, the present invention is not limited to this.
For example, when the lX-YlO value approaches N/4 or 3N/4, a wealth+u signal may be output.
Furthermore, the comparator circuit (21) may add a certain offset value to the value of Y.

On the other hand, the video signal discrimination circuit of the present invention is not limited to the above-described embodiments, and it goes without saying that changes can be made without departing from the gist of the present invention.

〔Effect of the invention〕

As described above, the video signal discrimination circuit of the present invention can detect the phase of the horizontal synchronization signal at the time of change of the vertical synchronization signal with a resolution of 360 degrees.
/N, even if there is a periodic variation in the horizontal synchronization signal, by performing appropriate arithmetic comparison, it can be determined whether the video signal is interlaced or not, or if it is interlaced, whether it is an even number or an odd number. Fields can be accurately determined.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the video signal discrimination circuit of the present invention, FIG. 2 is a signal waveform diagram of each part when the video signal in the example in FIG. 1 is non-interlaced, and FIG. FIG. 4 is a configuration diagram showing an example of a conventional discrimination circuit; FIG. 5 is a signal waveform diagram of various parts in the conventional example of FIG. 4;
FIG. 6 is a block diagram showing another example of a conventional discrimination circuit. (15) is a PLL circuit, (16) is a divide-by-N counter, (
17) and (18) are latch circuits, (19) is a D-type flip-flop, (20) is a comparison circuit, and (21) is another comparison circuit.

Claims (1)

[Claims] a PLL circuit that receives a horizontal synchronization signal of the video signal as one input; a counter that divides the output of the PLL circuit and receives the divided signal as the other input of the PLL circuit; and a vertical synchronization signal of the video signal. a first latch circuit that latches the count value of the counter in synchronization with the vertical synchronization signal; and a second latch circuit that latches the held value of the first latch circuit in synchronization with the vertical synchronization signal; It is characterized by determining whether the video signal is interlaced or not, and if it is interlaced, whether it is an even field or an odd field, based on the values held in the first and second latch circuits. Video signal discrimination circuit.