KR940022714A - 결점 개선된 CoSi₂를 형성함으로써 디이프 서브 - 마이크론 MOSFET에서 규화접합을 형성하는 방법 - Google Patents
결점 개선된 CoSi₂를 형성함으로써 디이프 서브 - 마이크론 MOSFET에서 규화접합을 형성하는 방법 Download PDFInfo
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- KR940022714A KR940022714A KR1019940004163A KR19940004163A KR940022714A KR 940022714 A KR940022714 A KR 940022714A KR 1019940004163 A KR1019940004163 A KR 1019940004163A KR 19940004163 A KR19940004163 A KR 19940004163A KR 940022714 A KR940022714 A KR 940022714A
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- 238000000034 method Methods 0.000 title claims abstract description 22
- 229910021332 silicide Inorganic materials 0.000 title claims description 10
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 title claims description 10
- 229910018999 CoSi2 Inorganic materials 0.000 title abstract 3
- 230000007547 defect Effects 0.000 title abstract 2
- 229910017052 cobalt Inorganic materials 0.000 claims abstract 18
- 239000010941 cobalt Substances 0.000 claims abstract 18
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims abstract 18
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract 16
- 229910052710 silicon Inorganic materials 0.000 claims abstract 16
- 239000010703 silicon Substances 0.000 claims abstract 16
- 238000004544 sputter deposition Methods 0.000 claims abstract 14
- 150000002500 ions Chemical class 0.000 claims abstract 12
- 238000004140 cleaning Methods 0.000 claims abstract 11
- 239000002184 metal Substances 0.000 claims abstract 10
- 229910052751 metal Inorganic materials 0.000 claims abstract 10
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims abstract 8
- 238000009792 diffusion process Methods 0.000 claims abstract 6
- 238000000151 deposition Methods 0.000 claims 7
- 229910019001 CoSi Inorganic materials 0.000 claims 5
- 230000008021 deposition Effects 0.000 claims 5
- 238000005245 sintering Methods 0.000 claims 2
- 238000005242 forging Methods 0.000 claims 1
- 150000003377 silicon compounds Chemical class 0.000 claims 1
- 230000015572 biosynthetic process Effects 0.000 abstract 1
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
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- Y10S148/00—Metal treatment
- Y10S148/017—Clean surfaces
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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Abstract
디프 서브미크론 결점이 개선된 CoSi2형성 및 개선된 규화 접합을 제공하는 방법, 확산 윈도우를 가진 실리콘 웨이퍼는 플루오르화 수소산으로 첫 번째로 사전 세척된다. HF사전 세척후에, 실리콘 웨이퍼는 통상적인 코발트 스퍼터링 용기안으로 이송되고, 극히 얕은 손상 영역을 형성하도록 낮은 에너지 Ar+이온으로의 충돌에 의해 스퍼터링 세척된다. 스퍼터링 세척후, 스퍼터링 용기에서 실리콘 웨이퍼를 옮기지 않고 코발트 금속이 실온에서 실리콘 웨이퍼 위에 증착되어 CoSi2층이 확산 윈도우 안에 형성된다.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제5도는 본 발명의 실시예에 따른 디이프 서브-마이크론 MOSFET에서 규화집합을 형성하는 방법에 대한 흐름도를도시한다.
Claims (16)
- 디프 서브미크론 MOSFET 규화 접합을 형성하는 방법에 있어서, 실리콘 웨이퍼를 플루오르화 수소산으로 사전 세척하는 단계와, 사전세척후, 실리콘 웨이퍼를 스퍼터링 용기에 이송하는 단계와 : 스퍼터링용기에서, 실리콘 웨이퍼를 저 에너지 Ar+이온의 충돌로 스퍼터링 세척하는 단계와 : 스퍼터링 세척후 스퍼터링 용기에서 실리콘 웨이퍼를 옮기지 않은채, 코발트 규화물(CoSi2)층을 형성하도록 실리콘 웨이퍼 위에 코발트 금속을 증착하는 단계를 포함하는 것을 특징으로 하는 디프 서브미크론 MOSFET에 규화 접합을 형성하는 방법.
- 제1항에 있어서, 저 에너지 Ar+이온으로의 충돌은 1μA의 약 1,5keV에서 일어나는 것을 특징으로 하는 디프 서브미크론 MOSFET에 규화 접합을 형성하는 방법.
- 제1항에 있어서, 코발트 금속의 증착은 실온에서 수행되는 것을 특징으로 하는 디프 서브미크론 MOSFET에서 규화 접합을 형성하는 방법.
- 제1항에 있어서, CoSi2층은 어떤 추후 소결단계없이 코발트 금속의 증착동안 형성되는 것을 특징으로 하는 디프 서브미크론 MOSFET규화 접합을 형성하는 방법.
- 제2항에 있어서, 저 에너지 Ar+이온의 충돌은 15분 정도 동안에 일어나는 것을 특징으로 하는 디프 서브미크론 MOSFET에서 규화 접합을 형성하는 방법.
- 제4항에 있어서, 코발트 금속의 증착동안 형성된 CoSi2은 30 나노미터 이하의 깊이인 것을 특징으로 하는 디프 서브미크론 MOSFET규화 접합을 형성하는 방법.
- 서브미크론 MOSFET에 있어서, 평방미터당 5오옴정도의 낮은 시트저항 및 1500옹스트롱 이하의 접합을 가지며, 규소화합물 덩어리가 없는 것을 특징으로 하는 서브미크론 MOSFET.
- 디프 서브미크론 MOSFET에서 규화 접합을 형성하는 방법에 있어서, 실리콘 웨이퍼를 플루오르화 수소산으로 사전 세척하는 단계와 : 사전 세척후, 실리콘 웨이퍼를 코발트 스퍼터링 용기안으로 이송하는 단계와 : 코발트 스퍼터링 용기안에서, 실리콘 웨이퍼를 낮은 에너지 이온으로 스퍼터링 세척하는 단계와 : 스퍼터링 세척후, 어떤 추후 소결단계도 없이 코발트 규화물(CoSi2)층을 형성하기 위하여 실리콘 웨이퍼 위에 코발트 금속을 증착하는 단계를 포함하는 것을 특징으로 하는 디프 서브미크론 MOSFET에서 규화 접합을 형성하는 방법.
- 제8항에 있어서, 실리콘 웨이퍼는 상기 웨이퍼 위에 형성된 확산 윈도우를 가지며, 확산 윈도우에 의해 노출된 실리콘 웨이퍼의 7개의 단조층에 대해 단기 3개층만이 손상을 입는 것을 특징으로 하는 디프 서브미크론 MOSFET에서 규화 접합을 형성하는 방법.
- 제8항에 있어서, 낮은 에너지 이온으로의 충돌은 1μA의 약 1.5keV에서 Ar+이온을 사용해서 수행되는 것을 특징으로 하는 디프 서브미크론 MOSFET에서 규화 접합을 형성하는 방법.
- 제8항에 있어서, 코발트 금속의 증착은 실온에서 수행되는 것을 특징으로 하는 디프 서브미크론 MOSFET에서 규화 접합을 형성하는 방법.
- 제8항에 있어서, 낮은 에너지 이온으로의 충돌은 약 10 내지 15분동안 약 1μA의 약 1.5keV에서 Ar+이온을 사용해서 수행되는 것을 특징으로 하는 디프 서브미크론 MOSFET에서 규화 접합을 형성하는 방법.
- 제8항에 있어서, 코발트 금속의 증착동안 형성된 CoSi2은 30 나노미터 이하의 깊이를 가지는 것을 특징으로 하는 디프 서브미크론 MOSFET에서 규화 접합을 형성하는 방법.
- 제10항에 있어서, 낮은 에너지 이온으로의 충돌은 10분 또는 그 이하동안 일어나며, Ar+이온을 사용해서 수행되는 것을 특징으로 하는 디프 서브미크론 MOSFET에서 규화 접합을 형성하는 방법.
- 디프 서브미크론 MOSFET에서 규화 접합을 형성하는 방법에 있어서, 웨이퍼에 형성된 확산 윈도우를 가진 실리콘 웨이퍼를 플루오르화 수소산으로 사전 처리하는 단계와 : 사전처리후, 실리콘 웨이퍼를 코발트 스퍼터링 용기에 이송하는 단계와 : 코발트 스퍼터링 용기안에서, 확산 윈도우안에 있는 실리콘 단조층 정도만을 손상하도록 Ar+이온으로의 충돌에 의해 실리콘 웨이퍼를 스퍼터링 세척하는 단계와 : 스퍼터링 세척후 웨이퍼를 코발트 스퍼터링 용기에서 옮기지 않은채 실리콘 웨이퍼 위에 코발트 금속을 증착하는 단계를 포함하는 것을 특징으로 하는 디프 서브미크론 MOSFET에서 규화 접합을 형성하는 방법.
- 제15항에 있어서, 코발트 금속은 증착은 실온에서 수행되는 것을 특징으로 하는 디프 서브미크론 MOSFET에서 규화 접합을 형성하는 방법.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
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US8/026,944 | 1993-03-05 | ||
US08/026,944 | 1993-03-05 | ||
US08/026,944 US5344793A (en) | 1993-03-05 | 1993-03-05 | Formation of silicided junctions in deep sub-micron MOSFETs by defect enhanced CoSi2 formation |
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KR940022714A true KR940022714A (ko) | 1994-10-21 |
KR100364919B1 KR100364919B1 (ko) | 2003-02-26 |
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KR1019940004163A KR100364919B1 (ko) | 1993-03-05 | 1994-03-04 | 결함이개선된CoSi2형성에의한디프(deep)서브-미크론MOSFET의실리사이드화접합부형성방법및MOSFET반도체소자 |
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EP (1) | EP0616361B1 (ko) |
JP (1) | JPH06302545A (ko) |
KR (1) | KR100364919B1 (ko) |
AT (1) | ATE194729T1 (ko) |
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US5824600A (en) * | 1993-01-19 | 1998-10-20 | Lg Semicon Co., Ltd. | Method for forming a silicide layer in a semiconductor device |
JP2611726B2 (ja) * | 1993-10-07 | 1997-05-21 | 日本電気株式会社 | 半導体装置の製造方法 |
US5650040A (en) * | 1995-11-30 | 1997-07-22 | Micron Technology, Inc. | Interfacial etch of silica to improve adherence of noble metals |
KR0172559B1 (ko) * | 1995-12-29 | 1999-03-30 | 김주용 | 반도체소자의 제조방법 |
GB2320130B (en) * | 1996-08-09 | 2001-11-07 | United Microelectronics Corp | Improved self-ligned silicide manufacturing method |
NL1004812C2 (nl) * | 1996-12-18 | 1998-06-19 | United Microelectronics Corp | Verbeterde werkwijze voor het vervaardigen van autonoom uitgelijnd metaalsilicide. |
EP0865077A1 (en) * | 1997-03-14 | 1998-09-16 | Interuniversitair Micro-Elektronica Centrum Vzw | Method for the formation of a thin metal silicide layer on a Si substrate, and use thereof in detector applications |
SE511721C2 (sv) * | 1997-06-18 | 1999-11-15 | Ericsson Telefon Ab L M | Substrat för integrerade högfrekvenskretsar samt förfarande för substratframställning |
EP0890979A1 (fr) | 1997-07-11 | 1999-01-13 | EM Microelectronic-Marin SA | Méthode d'optimisation de procédés de dépÔt et de gravure, en fonction de la structure d'une couche polycristalline à déposer et à graver |
TW383463B (en) | 1998-06-01 | 2000-03-01 | United Microelectronics Corp | Manufacturing method for dual damascene structure |
US6680248B2 (en) | 1998-06-01 | 2004-01-20 | United Microelectronics Corporation | Method of forming dual damascene structure |
US6383905B2 (en) * | 1998-07-31 | 2002-05-07 | Stmicroelectronics, Inc. | Formation of micro rough poly surface for low sheet resistance salicided sub-quarter micron poly lines |
US6355580B1 (en) | 1998-09-03 | 2002-03-12 | Micron Technology, Inc. | Ion-assisted oxidation methods and the resulting structures |
US6251777B1 (en) | 1999-03-05 | 2001-06-26 | Taiwan Semiconductor Manufacturing Company | Thermal annealing method for forming metal silicide layer |
US6335294B1 (en) * | 1999-04-22 | 2002-01-01 | International Business Machines Corporation | Wet cleans for cobalt disilicide processing |
US6184132B1 (en) | 1999-08-03 | 2001-02-06 | International Business Machines Corporation | Integrated cobalt silicide process for semiconductor devices |
US7037371B1 (en) * | 1999-10-04 | 2006-05-02 | Matsushita Electric Industrial Co., Ltd. | Method for fabricating semiconductor device |
KR100398041B1 (ko) * | 2000-06-30 | 2003-09-19 | 주식회사 하이닉스반도체 | 반도체 소자의 에피 채널 형성 방법 |
KR100343653B1 (ko) * | 2000-09-22 | 2002-07-11 | 윤종용 | 금속 실리사이드층을 갖는 반도체 장치 및 그 제조방법 |
JP2002134632A (ja) * | 2000-10-20 | 2002-05-10 | Hitachi Ltd | 半導体集積回路装置の製造方法 |
US6475893B2 (en) * | 2001-03-30 | 2002-11-05 | International Business Machines Corporation | Method for improved fabrication of salicide structures |
US6399493B1 (en) * | 2001-05-17 | 2002-06-04 | Advanced Micro Devices, Inc. | Method of silicide formation by silicon pretreatment |
US6743721B2 (en) * | 2002-06-10 | 2004-06-01 | United Microelectronics Corp. | Method and system for making cobalt silicide |
US6846359B2 (en) * | 2002-10-25 | 2005-01-25 | The Board Of Trustees Of The University Of Illinois | Epitaxial CoSi2 on MOS devices |
US20060240666A1 (en) * | 2005-04-20 | 2006-10-26 | Chao-Ching Hsieh | Method of forming silicide |
US20090004851A1 (en) * | 2007-06-29 | 2009-01-01 | Taiwan Semiconductor Manufacturing Co., Ltd. | Salicidation process using electroless plating to deposit metal and introduce dopant impurities |
US7482217B1 (en) | 2007-12-03 | 2009-01-27 | Spansion Llc | Forming metal-semiconductor films having different thicknesses within different regions of an electronic device |
US9960135B2 (en) * | 2015-03-23 | 2018-05-01 | Texas Instruments Incorporated | Metal bond pad with cobalt interconnect layer and solder thereon |
US9576908B1 (en) * | 2015-09-10 | 2017-02-21 | Taiwan Semiconductor Manufacturing Co., Ltd. | Interconnection structure, fabricating method thereof, and semiconductor device using the same |
Family Cites Families (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3661747A (en) * | 1969-08-11 | 1972-05-09 | Bell Telephone Labor Inc | Method for etching thin film materials by direct cathodic back sputtering |
US4164461A (en) * | 1977-01-03 | 1979-08-14 | Raytheon Company | Semiconductor integrated circuit structures and manufacturing methods |
US4522485A (en) * | 1978-04-24 | 1985-06-11 | Canon Kabushiki Kaisha | Copying machine including a dielectric covered metal reflective device |
US4261764A (en) * | 1979-10-01 | 1981-04-14 | The United States Of America As Represented By The United States Department Of Energy | Laser method for forming low-resistance ohmic contacts on semiconducting oxides |
US4495510A (en) * | 1980-10-22 | 1985-01-22 | Hughes Aircraft Company | Improved superconductor/semiconductor junction structures |
US4545116A (en) * | 1983-05-06 | 1985-10-08 | Texas Instruments Incorporated | Method of forming a titanium disilicide |
US4579609A (en) * | 1984-06-08 | 1986-04-01 | Massachusetts Institute Of Technology | Growth of epitaxial films by chemical vapor deposition utilizing a surface cleaning step immediately before deposition |
US4585517A (en) * | 1985-01-31 | 1986-04-29 | Motorola, Inc. | Reactive sputter cleaning of semiconductor wafer |
US4647361A (en) * | 1985-09-03 | 1987-03-03 | International Business Machines Corporation | Sputtering apparatus |
US4647494A (en) * | 1985-10-31 | 1987-03-03 | International Business Machines Corporation | Silicon/carbon protection of metallic magnetic structures |
GB2214708A (en) * | 1988-01-20 | 1989-09-06 | Philips Nv | A method of manufacturing a semiconductor device |
KR910005401B1 (ko) * | 1988-09-07 | 1991-07-29 | 경상현 | 비결정 실리콘을 이용한 자기정렬 트랜지스터 제조방법 |
US4886765A (en) * | 1988-10-26 | 1989-12-12 | American Telephone And Telegraph Company, At&T Bell Laboratories | Method of making silicides by heating in oxygen to remove contamination |
US4908334A (en) * | 1989-01-24 | 1990-03-13 | The United States Of America As Represented By The United States Department Of Energy | Method for forming metallic silicide films on silicon substrates by ion beam deposition |
US5047367A (en) * | 1990-06-08 | 1991-09-10 | Intel Corporation | Process for formation of a self aligned titanium nitride/cobalt silicide bilayer |
US5023201A (en) * | 1990-08-30 | 1991-06-11 | Cornell Research Foundation, Inc. | Selective deposition of tungsten on TiSi2 |
US5162259A (en) * | 1991-02-04 | 1992-11-10 | Motorola, Inc. | Method for forming a buried contact in a semiconductor device |
-
1993
- 1993-03-05 US US08/026,944 patent/US5344793A/en not_active Expired - Lifetime
- 1993-12-11 TW TW082110522A patent/TW267242B/zh not_active IP Right Cessation
-
1994
- 1994-03-03 EP EP94103190A patent/EP0616361B1/en not_active Expired - Lifetime
- 1994-03-03 AT AT94103190T patent/ATE194729T1/de not_active IP Right Cessation
- 1994-03-03 DE DE69425171T patent/DE69425171D1/de not_active Expired - Lifetime
- 1994-03-04 KR KR1019940004163A patent/KR100364919B1/ko not_active IP Right Cessation
- 1994-03-04 JP JP6060049A patent/JPH06302545A/ja active Pending
-
1996
- 1996-11-05 US US08/744,132 patent/US5780929A/en not_active Expired - Lifetime
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US5344793A (en) | 1994-09-06 |
EP0616361A1 (en) | 1994-09-21 |
ATE194729T1 (de) | 2000-07-15 |
KR100364919B1 (ko) | 2003-02-26 |
TW267242B (ko) | 1996-01-01 |
EP0616361B1 (en) | 2000-07-12 |
JPH06302545A (ja) | 1994-10-28 |
US5780929A (en) | 1998-07-14 |
DE69425171D1 (de) | 2000-08-17 |
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