KR940012511A - Etching Method in Manufacturing Semiconductor Device - Google Patents

Etching Method in Manufacturing Semiconductor Device Download PDF

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Publication number
KR940012511A
KR940012511A KR1019920021234A KR920021234A KR940012511A KR 940012511 A KR940012511 A KR 940012511A KR 1019920021234 A KR1019920021234 A KR 1019920021234A KR 920021234 A KR920021234 A KR 920021234A KR 940012511 A KR940012511 A KR 940012511A
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KR
South Korea
Prior art keywords
semiconductor device
etching method
etching
manufacturing semiconductor
contact hole
Prior art date
Application number
KR1019920021234A
Other languages
Korean (ko)
Other versions
KR960002071B1 (en
Inventor
황현상
Original Assignee
문정환
금성일렉트론 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 문정환, 금성일렉트론 주식회사 filed Critical 문정환
Priority to KR1019920021234A priority Critical patent/KR960002071B1/en
Publication of KR940012511A publication Critical patent/KR940012511A/en
Application granted granted Critical
Publication of KR960002071B1 publication Critical patent/KR960002071B1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

본 발명은 반도체 장치 제작시에 콘택홀 형성등과 같이 소정깊이까지만 정확하게 에칭을 할 수 있는 신규의 에칭방법에 관한 것이다. 종래의 기술에서는 콘택홀 형성은 일시에 엔드-포인트(end-point)까지 식각을 하였기 때문에 필요이상으로 과도하게 에칭되어 소자의 성능저하를 야기했지만, 본 발명에서는 엔드-포인트전에 미리 진성 실리콘층(10)을 매립하여 식각이 단계별로 행해지도록 함으로써 필요이상 에칭되는 것을 방지하는 효과가 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a novel etching method that can accurately etch only a predetermined depth, such as contact hole formation, during semiconductor device fabrication. In the prior art, since the contact hole was etched to the end-point at a time, it was excessively etched more than necessary to cause the deterioration of the device. There is an effect of preventing the etching more than necessary by embedding 10) so that etching is performed step by step.

Description

반도체 장치 제조시의 에칭 방법Etching Method in Manufacturing Semiconductor Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도는 본 발명의 방법에 따른 반도체 장치의 에칭 공정시에 양호한 에칭상태를 나타낸 도면.2 is a view showing a good etching state in the etching process of the semiconductor device according to the method of the present invention.

Claims (1)

반도체 장치제조시 소정깊이까지의 콘택홀 형성을 위한 에칭방법에 있어서, 상기 소정깊이에 도달하기 전에 MOT-산화막(7)위에 300∼1000Å두께의 진성실리콘층(10)을 매립한후 에칭을 행하는 것을 특징으로 하는 반도체 장치 제조시의 에칭방법.An etching method for forming a contact hole up to a predetermined depth in the manufacture of a semiconductor device, in which an intrinsic silicon layer 10 having a thickness of 300 to 1000 kPa is buried on the MOT-oxide film 7 before the predetermined depth is reached. An etching method in the manufacture of a semiconductor device. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019920021234A 1992-11-12 1992-11-12 Contact forming method of semiconductor device KR960002071B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019920021234A KR960002071B1 (en) 1992-11-12 1992-11-12 Contact forming method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019920021234A KR960002071B1 (en) 1992-11-12 1992-11-12 Contact forming method of semiconductor device

Publications (2)

Publication Number Publication Date
KR940012511A true KR940012511A (en) 1994-06-23
KR960002071B1 KR960002071B1 (en) 1996-02-10

Family

ID=19343008

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019920021234A KR960002071B1 (en) 1992-11-12 1992-11-12 Contact forming method of semiconductor device

Country Status (1)

Country Link
KR (1) KR960002071B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100604779B1 (en) * 1999-07-10 2006-07-26 삼성전자주식회사 Semiconductor device comprising self-align contact and method for manufacturing the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100604779B1 (en) * 1999-07-10 2006-07-26 삼성전자주식회사 Semiconductor device comprising self-align contact and method for manufacturing the same

Also Published As

Publication number Publication date
KR960002071B1 (en) 1996-02-10

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