KR940010331A

KR940010331A - Method of forming uneven capacitor of semiconductor device

Info

Publication number: KR940010331A
Application number: KR1019920019290A
Authority: KR
Inventors: 이태국; 박성남
Original assignee: 김주용; 현대전자산업 주식회사
Priority date: 1992-10-20
Filing date: 1992-10-20
Publication date: 1994-05-26

Abstract

본 발명은 DRAM의 캐패시터용량을 증가 시키는 것으로, 특히 캐패시터의 면적을 증가 시키는 반도체 소자의 요철 캐패시터 형성 방법에 관한 것으로, 반도체 기판(11)에 소정의 간격으로 필드 산화막(1), 게이트 전극(2), 스페이서 산화막(3)을 갖는 반도체 소자의 요철 캐패시터 형성 방법에 있어서, 절연막(4,5)을 도포하고 제1폴리실리콘막(6)은 증착한 후에 감광막(7)을 패턴하여 현상하여 캐패시터가 형성되는 소오스 상부에 위치한 제1폴리실리콘막(6) 일부를 식각하는 제1단계, 상기 제1단계 후에 반도체기판(11)과 콘택홀을 형성하여 제2폴리실리콘막(8)을 증착하는 제2단계, 상기 제2단계 후에 상기 제2폴리실리콘막(8)과 잔류되어 있는 제1폴리실리콘막(6)을 다시 식각하여 요철(높이 ▽h, 길이 ▽1) 형태를 갖는 제1폴리실리콘막(6)을 형성하는 제3단계, 상기 제3단계 후에 유전막(5)과 제3폴리실리콘막(10)을 형성하는 캐패시터를 형성하는 제4단계를 구비하여 이루어지는 것을 특징으르 하는 반도체 소자의 요전 캐패시터 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an increase in the capacitance of a DRAM, and more particularly, to a method of forming an uneven capacitor of a semiconductor device which increases the area of a capacitor. In the method of forming the uneven capacitor of the semiconductor device having the spacer oxide film 3, the insulating films 4 and 5 are applied and the first polysilicon film 6 is deposited, and then the photosensitive film 7 is patterned and developed to form a capacitor. Forming a contact hole with the semiconductor substrate 11 after the first step of etching a portion of the first polysilicon film 6 positioned on the source on which the second polysilicon film 6 is formed, and depositing the second polysilicon film 8. After the second step and the second step, the second polysilicon film 8 and the remaining first polysilicon film 6 are etched again to form a first poly having an uneven shape (height ▽ h, length ▽ 1). A third step of forming the silicon film 6, the After step 3, the semiconductor device characterized in that the lazy formed by comprising a fourth step of forming a capacitor to form the dielectric layer 5 and the third polysilicon film 10 is directed to a method for forming a capacitor other day.

Description

Method of forming uneven capacitor of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명에 따른 DRAM 요철 캐패시터 제조 공정도,2 is a manufacturing process diagram of the DRAM uneven capacitor according to the present invention,

제3도는 제2도(e)의 평면도.3 is a plan view of FIG.

Claims

In the method of forming the uneven capacitor of a semiconductor device having the field oxide film 1, the gate bottom electrode 2, and the spacer oxide film 3 on the semiconductor substrate 11 at predetermined intervals, two insulating films 4 and 5 are sequentially applied. After the first polysilicon film 6 is deposited, the photoresist film 7 is patterned and developed to etch a portion of the first polysilicon film 6 positioned on the source where the capacitor is formed, after the first step. A second step of depositing a second polysilicon film 8 by forming a contact hole with the semiconductor substrate 11, and a first polysilicon film remaining with the second polysilicon film 8 after the second step ( 6) is again etched to form a first polysilicon film 6 having irregularities (height? H depth? 1), and after the third step, the dielectric film 9 and the third polysilicon film 10 Peninsula, characterized in that it comprises a fourth step of forming a capacitor to form a) The method of forming the unevenness capacitor element.

※ Note: The disclosure is based on the initial application.