KR930015097A - Thin Film Transistor Manufacturing Method - Google Patents

Thin Film Transistor Manufacturing Method Download PDF

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Publication number
KR930015097A
KR930015097A KR1019910025521A KR910025521A KR930015097A KR 930015097 A KR930015097 A KR 930015097A KR 1019910025521 A KR1019910025521 A KR 1019910025521A KR 910025521 A KR910025521 A KR 910025521A KR 930015097 A KR930015097 A KR 930015097A
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KR
South Korea
Prior art keywords
semiconductor layer
gate
forming
patterning
substrate
Prior art date
Application number
KR1019910025521A
Other languages
Korean (ko)
Inventor
김정현
Original Assignee
이헌조
주식회사 금성사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 이헌조, 주식회사 금성사 filed Critical 이헌조
Priority to KR1019910025521A priority Critical patent/KR930015097A/en
Publication of KR930015097A publication Critical patent/KR930015097A/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Thin Film Transistor (AREA)

Abstract

본 발명은 마스크 사용 횟수를 감소시켜 수율을 향상시킬 수 있는 박막 트랜지스터 제조 방법에 관한 것으로 종래 공정에서는 마스크를 많이 사용하여 공정이 복잡하고 각층간의 정렬시 미스 정렬이 되기 쉬워 수율이 감소되는 문제가 있어 본 발명에서는 기판(1)에 게이트(2)를 형성하는 공정, 게이트 절연막(4), 제1반도체층(5), 에치스톱퍼(11), 감광막(7)을 형성하는 공정, 기판(1)쪽에서 자외선을 조사하여 에치 스톱퍼(11)을 패터닝하는 공정, 제2반도체층(6)을 패터닝하는 공정, 투면전극(9)을 증착하여 화소를 형성하고 베리어 금속(13)과 소오스/드레인 전극(8)을 형성하여 패터닝하는 공정, 채널 형성을 위해 채널 부위(14)위의 제2반도체층(6)을 제거하는 공정을 차례로 실시하여 마스크 공정을 감소시켜 제조 방법을 개선한 것이다.The present invention relates to a thin film transistor manufacturing method that can improve the yield by reducing the number of times the mask used in the conventional process has a problem that the process is complicated by using a lot of mask in the conventional process, easy to be mis-aligned when the alignment between the layers, the yield is reduced In the present invention, the process of forming the gate 2 on the substrate 1, the process of forming the gate insulating film 4, the first semiconductor layer 5, the etch stopper 11, the photosensitive film 7, the substrate (1) A step of patterning the etch stopper 11 by irradiating ultraviolet rays from the side, a step of patterning the second semiconductor layer 6, and depositing a projection electrode 9 to form a pixel, and forming a barrier metal 13 and a source / drain electrode ( 8) forming and patterning, and then removing the second semiconductor layer 6 on the channel portion 14 to form a channel in order to reduce the mask process to improve the manufacturing method.

Description

박막 트랜지스터 제조 방법Thin Film Transistor Manufacturing Method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도는 본 발명의 박막 트랜지스터의 공정단면도.2 is a process cross-sectional view of the thin film transistor of the present invention.

Claims (3)

기판(1)위에 게이트(2)와 산화막(3)을 형성하는 공정과, 상기 전면에 게이트 절연막(4), 제1반도체층(5), 에치 스톱퍼(11), 감광막(7)을 차례로 형성하는 공정과, 상기 기판(1)쪽으로부터 자외선을 조사하여 게이트 패턴을 마스트로 에칭 스톱퍼(11)를 패터닝하는 공정과, 전표면에 제2반도체층(6)과 감광막(12)을 도포하고 기판(1)쪽으로부터 자외선을 조사하여 제2반도체층(6)을 패터닝하는 공정과, 투면전극(9)을 증착하여 화소를 형성하고 배리어 금속(13)과 소오스/드레인 전극(8)을 형성하여 패터닝하는 공정과, 채널 형성을 위해 채널부위(14)위의 제2반도체층(6)을 제거하는 공정을 차례로 실시하여서 이루어지는 박막 트랜지스터 제조방법.Forming a gate 2 and an oxide film 3 on the substrate 1, and sequentially forming a gate insulating film 4, a first semiconductor layer 5, an etch stopper 11, and a photoresist film 7 on the entire surface of the substrate 1. And a step of patterning the gate stopper 11 by etching the gate pattern by irradiating ultraviolet rays from the substrate 1 side, and applying the second semiconductor layer 6 and the photosensitive film 12 to the entire surface of the substrate. Patterning the second semiconductor layer 6 by irradiating ultraviolet rays from the (1) side, depositing the transmissive electrode 9 to form a pixel, and forming a barrier metal 13 and a source / drain electrode 8 A method of manufacturing a thin film transistor, comprising a step of patterning and a step of removing a second semiconductor layer (6) on a channel portion (14) to form a channel. 제1항에 있어서, 에치 스토퍼(11) 패턴을 게이트(2) 패턴보다 1㎛∼2㎛ 수축되게 형성하는 박막 트랜지스터 제조 방법.The method of claim 1, wherein the etch stopper (11) pattern is formed to shrink by 1 µm to 2 µm than the gate (2) pattern. 제1항에 있어서, 제2반도체층(6)의 면적을 게이트 면적 크기로 줄인 박막 트랜지스터 제조 방법.The method of claim 1, wherein the area of the second semiconductor layer (6) is reduced to the size of the gate area. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019910025521A 1991-12-30 1991-12-30 Thin Film Transistor Manufacturing Method KR930015097A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019910025521A KR930015097A (en) 1991-12-30 1991-12-30 Thin Film Transistor Manufacturing Method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910025521A KR930015097A (en) 1991-12-30 1991-12-30 Thin Film Transistor Manufacturing Method

Publications (1)

Publication Number Publication Date
KR930015097A true KR930015097A (en) 1993-07-23

Family

ID=40977260

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910025521A KR930015097A (en) 1991-12-30 1991-12-30 Thin Film Transistor Manufacturing Method

Country Status (1)

Country Link
KR (1) KR930015097A (en)

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