KR930014075A - Modular system for controlling burst transfer of data between bus and memory - Google Patents

Modular system for controlling burst transfer of data between bus and memory Download PDF

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Publication number
KR930014075A
KR930014075A KR1019910024512A KR910024512A KR930014075A KR 930014075 A KR930014075 A KR 930014075A KR 1019910024512 A KR1019910024512 A KR 1019910024512A KR 910024512 A KR910024512 A KR 910024512A KR 930014075 A KR930014075 A KR 930014075A
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KR
South Korea
Prior art keywords
data
bus
bit
module
controlling
Prior art date
Application number
KR1019910024512A
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Korean (ko)
Inventor
최장식
김상범
이훈복
박치항
Original Assignee
경상현
재단법인 한국전자통신연구소
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Priority to KR1019910024512A priority Critical patent/KR930014075A/en
Publication of KR930014075A publication Critical patent/KR930014075A/en

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Abstract

본 발명은 병렬처리 시스템을 구성하는 노드의 내부구조에서 64비트의 버스(MBUS)와 32비트의 노드 메모리사이의 데이타의 입출력시 버스의 클럭에 동기화 되면서 64비트 데이타 폭을 최대한 이용하기 위해 버스트모드(burst mode)전송을 효율적으로 지원하기 위한 버스와 메모리사이에서 데이타의 버스트 전송을 제어하기 위한 모듈 시스템을 제공하는 것이다.The present invention is a burst mode for maximizing the 64-bit data width while being synchronized to the clock of the bus during input and output of data between the 64-bit bus (MBUS) and 32-bit node memory in the internal structure of the node constituting the parallel processing system (burst mode) Provides a modular system for controlling the burst transfer of data between the bus and the memory to support transfer efficiently.

Description

버스와 메모리사이에서 데이타의 버스트 전송을 제어하기 위한 모듈시스템Modular system for controlling burst transfer of data between bus and memory

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 노드 메모리 인터페이스를 위한 본 발명의 도면.1 is a diagram of the present invention for a node memory interface.

제2도는 Burst모듈의 동작을 위한 블럭구성도를 나타낸 도면.2 is a block diagram for the operation of the burst module.

제5도는 버스트와 관련한 모듈간의 동작 흐름도.5 is a flowchart of operation between modules in relation to a burst.

Claims (1)

데이타의 버스트 전송을 제어하기위한 모듈 시스템에 있어서, 버스트 모드전송을 지원하기위해 노드 메모리의 뱅크를 연속적으로 선택하고, 입출력 과정의 중간단계에 놓여 있는 래치를 제어하고, 버스트의 상태를 나타내어 입출력의 진행과 함께 그 상태를 바꾸어가는 모듈과, 노드 프로세서의 관여없이 새로운 주소를 연속적으로 버스트 기간동안 발생시키도륵 4개의 뱅크(bank)로 구성된 노드 메모리의 뱅크 선택을 위한 상태머신으로 PAL로 구현된 모듈과, 트랜잭션의 크기에 따라 해당 값이 세팅되어 데이타의 입출력이 완료됨을 알리는 신호에 따라값이 하나섹 감소하여 트랜잭션의 끝을 결정하는 32비트카운터와 2변의 중간단계 ACK(응답)신호를 받아 하나의 Pinal-ACK(응답)신호를 내보내는 모듈과, 64비트 버스와 32비트의 데이타 폭을 갖는 메모리사이에서 데이타입출력시 데이타를 잠시 보관하기위한 64비트 래치와 트랜잭션의 유형과 크기에 따라 데이타 래치를 이루는 각 래치들의 개별적, 그룹적 제어를 동시에 제공하는 모듈에 의하여 버스트 모드 전송을 효율적으로 지원하도록 함을 특징으로하는 버스와 메모리 사이에서 데이타의 버스트 전송을 제어하기 위한 모듈시스템.In a modular system for controlling burst transfer of data, successively selecting a bank of node memories to support burst mode transfer, controlling a latch placed in the middle of the input / output process, and indicating the status of bursts A module that changes its state as it progresses, and a state machine for bank selection of node banks consisting of four banks that generates new addresses continuously during burst periods without involvement of the node processor. The value is set according to the module and the size of the transaction. The value is decreased by one section according to the signal indicating completion of input / output of the data, and receives the 32-bit counter which determines the end of the transaction and the middle side ACK signal of two sides. Between a module that emits one pinal-ACK signal, a 64-bit bus and a 32-bit data width In order to efficiently support burst mode transfer by a module that simultaneously provides 64-bit latches to temporarily hold data during data input and output, and individual and group control of each latch forming a data latch according to the type and size of a transaction. A modular system for controlling the burst transfer of data between a bus and a memory. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019910024512A 1991-12-26 1991-12-26 Modular system for controlling burst transfer of data between bus and memory KR930014075A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019910024512A KR930014075A (en) 1991-12-26 1991-12-26 Modular system for controlling burst transfer of data between bus and memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910024512A KR930014075A (en) 1991-12-26 1991-12-26 Modular system for controlling burst transfer of data between bus and memory

Publications (1)

Publication Number Publication Date
KR930014075A true KR930014075A (en) 1993-07-22

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KR1019910024512A KR930014075A (en) 1991-12-26 1991-12-26 Modular system for controlling burst transfer of data between bus and memory

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KR (1) KR930014075A (en)

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