KR0163140B1 - A circuit for jointly accessing a memory using a general sram - Google Patents

Abstract

The present invention relates to a memory sharing circuit using a general SRAM, including a general SRAM (10); A microprocessor (20) for irregularly accessing the SRAM (10); A real time controller 30 for accessing the SRAM 10 at a predetermined cycle and outputting a control signal for the microprocessor 20 to access the SRAM 10 at the remaining cycle; A buffer 40 operated by the control signal; And a mediation section (50) for receiving the control signal and outputting a data strobe recognition signal to arbitrate access to the microprocessor (20), wherein the real time control section (30) comprises: a timer (32); An SRAM controller 34 for accessing the SRAM 10 at a predetermined period; The buffer controller 36 outputs an enable signal to the buffer 40 at a predetermined period and outputs an access permission signal to the arbitration unit 50. The two processors share a general SRAM to provide a memory at regular intervals. The advantage of maximizing real-time transmission is by alternating access control.

Description

Memory sharing circuit using general SRAM

1 is a block diagram of a memory sharing circuit using a general SRAM according to the present invention.

2 is a timing diagram of a real time controller in a memory sharing circuit using a general SRAM according to the present invention.

3 is a timing diagram of a microprocessor in a memory sharing circuit using a general SRAM according to the present invention.

* Explanation of symbols for main parts of the drawings

10: SRAM 20: Microprocessor

30: real time control unit 32: timer

34: SRAM control unit 36: Buffer control unit

40: buffer 50: arbitration unit

TECHNICAL FIELD The present invention relates to a memory sharing circuit, and more particularly, to a memory sharing circuit using a general SRAM in which a circuit for accessing a memory in real time and periodically and a microprocessor for accessing a memory periodically share a single SRAM.

Asynchronous transfer switches and other electronic switch or digital circuits often use a common SRAM, dual port SRAM, or DRAM to implement a circuit in which multiple processors share memory.

In general, memory sharing circuits are mainly implemented using dual port SRAMs, and are particularly applicable to memory and peripheral circuits used for reference tables in an asynchronous transfer switch.

In the case of using the dual port SRAM, the control method is the simplest of the three cases and does not require a separate arbitration circuit. However, the disadvantage is that it is expensive, has a small capacity compared to the general SRAM, and takes up more space than the capacity. there was.

In addition, DRAM can be equipped with a large capacity in a low-cost and narrow space, while the refresh circuit and the arbitration circuit is required, and if the small capacity memory is required, the procurement of parts is rather impossible.

In case of using a general SRAM, a medium space is required at a medium price and a medium arbitration circuit is required as compared to the above two cases.

In particular, in the case of using general SRAM or DRAM (except dual port SRAM), it is important to consider to select a method of constructing an arbitration circuit, and most importantly, a microprocessor requiring memory access, or There is real-time data required for PBA (Printed Board Assembly).

In this case, when a control signal is input to the memory through an arbitration circuit and data is output or input from the memory, a time delay occurs when the data is input or output from the memory by directly controlling the memory without passing through the arbitration circuit. It is not possible to apply to circuits that require transmission.

Therefore, real-time transmission is required, and other similar digital circuits, such as an asynchronous transmission mode exchanger using a reference table at regular intervals, require a circuit that can guarantee real-time differentness from the conventional arbitration apparatus.

Accordingly, in order to solve the problem as described above, the present invention provides a memory sharing circuit using a general SRAM that allows real time transmission while simultaneously controlling two processors alternately sharing a memory using a single general SRAM. The purpose is to provide.

A memory sharing circuit using a general SRAM according to the present invention for achieving the above object comprises a general SRAM for storing data; A microprocessor for initializing and randomly accessing the SRAM; A real time controller for accessing the SRAM at regular time intervals and outputting a control signal for the microprocessor to access the SRAM at other times; A buffer (40) operated by the control signal to allow the microprocessor (20) to access the memory (10) without colliding with a real-time controller (30); And an arbitration unit receiving the control signal and outputting a data strobe recognition signal to terminate the access of the microprocessor.

According to the present invention, the microprocessor and the real-time control unit share a single memory so that the memory can be accessed without data collision.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram of a circuit for sharing a memory using a general SRAM according to the present invention, which includes: a general SRAM 10 for storing data; A microprocessor (20) for initializing and randomly accessing the SRAM (10); A real time controller 30 for accessing the SRAM 10 at regular time intervals and outputting a control signal for the microprocessor 20 to access the SRAM 10 at other times; A buffer (40) operated by the control signal to allow the microprocessor (20) to access the memory (10) without colliding with the real-time controller (30); And an arbitration unit 50 for receiving the control signal and outputting a data strobe recognition signal to terminate the access of the microprocessor 20.

Here, the real time controller 30 includes a timer 32 for generating a predetermined timing; An SRAM control unit 34 outputting a control signal to the SRAM 10 and reading data of the SRAM 10 during a predetermined timing generated from the timer 32; And a buffer controller 36 that outputs an enable signal to the buffer 40 and a SRAM access permission signal to the arbitration unit 50 during a predetermined timing generated from the timer 32.

Next, the operation and effects of the present invention configured as described above will be described in detail.

The microprocessor 20 initializes the SRAM 10. In addition, the start may be arbitrarily performed in accessing the SRAM 10, but ends when the data strobe acknowledgment signal is received from the arbitration unit 50.

The buffer 40 serves to separate the data bus, the address bus and the control bus of the microprocessor 20 and the real-time controller 30. In general, the reason for installing the buffer 40 is the microprocessor 20. And the signals output from the real-time control unit 30 to the SRAM 10 do not collide with each other.

Although not shown in FIG. 1, it is assumed that all input / output ports of the real-time control unit 30 have a buffer built therein.

The real-time control unit 30 accesses the SRAM 10 at regular time intervals, and outputs an enable signal so that the buffer 40 can be operated at the remaining time, and the microprocessor 20 controls the SRAM 10. A permission signal is output to be accessed, and the real time controller 30 includes a timer 32, an SRAM controller 34, and a buffer controller 36.

The SRAM control unit 34 generates an SRAM control signal in synchronization with a synchronization signal (for example, 8T period) supplied from the timer 32 to read data of the SRAM 10. If the operation time of the SRAM control unit 34 is 64T, for example, other times do not operate. The microprocessor 20 may access the SRAM 10 during the time when the SRAM controller 34 is not operating, that is, 56T.

The buffer controller 36 enables a buffer enable signal to enable the buffer 40 so that the microprocessor 20 can access the SRAM 10 during the time when the SRAM controller 34 does not access the SRAM 10. At the same time giving the SRAM access grant signal to the arbitration unit 50, thereby terminating the SRAM access process by generating a data strobe acknowledgment signal for use by the microprocessor 20 to terminate the SRAM access cycle. .

That is, if the microprocessor 20 accesses the SRAM 10 while the SRAM access permission signal is 'low', the microprocessor 20 may immediately receive a data strobe acknowledgment signal from the arbitration unit 50 to terminate the cycle. If the microprocessor 20 accesses the SRAM 10 when the SRAM access permission signal is 'high', this period is a period during which the SRAM control unit 34 uses the SRAM 10, and thus the microprocessor 20 starts a cycle. You must not terminate and wait.

The arbitration unit 50 generates a data strobe acknowledgment signal that terminates the operation cycle of the microprocessor 20.

That is, when the microprocessor 20 outputs a control signal 'low' to access the SRAM 10, when the arbitration unit 50 receives the SRAM access permission signal having a 'low' level from the buffer controller 36. The arbitration unit 50 inverts the data strobe acknowledgment signal from 'high' to 'low', and when the microprocessor 20 detects the 'low' of the data strobe acknowledgment signal, it terminates one cycle and then outputs a control signal. Invert from 'low' to 'high'. Accordingly, when the control signal becomes 'high', the data strobe acknowledgment signal is restored to its original state from 'low' to 'high'.

2 is a timing diagram of a real time processor in a memory sharing circuit using a general SRAM according to the present invention.

The subject of the use of the SRAM 10 in the present invention is a real time control unit 30, which is a microprocessor via the buffer 40 to signal the data bus, the address bus, and the control bus of the SRAM 10 via the buffer 40. The mediation function can be achieved by controlling the buffer using a buffer enable signal, which is a control signal for the buffer 40, shared with the signals of the 20, and the SRAM 10 of the microprocessor 20 can be achieved. Regardless of the control of the control unit, the arbitration unit 50 causes the microprocessor to activate the SRAM access permission signal applied to the arbitration unit 50 while the real-time control unit 30 does not access the SRAM 10. (20) Allows the control cycle for the SRAM 10 to end.

At this time, as shown in FIG. 3, if the real time controller 30 accesses the SRAM 10 for about 8T, the timing diagram of the real time controller 30 is about 64T (1T: 1 cycle of the synchronous clock) as shown in FIG. During the other 56T, the real time control unit 30 cannot access the SRAM 10, and the microprocessor 20 can access the SRAM 10 during this 56T period.

That is, while the buffer enable signal and the SRAM access enable signal are at the 'high' level as shown in (c) and (d) of FIG. 2, the chip select (CE) as shown in (e) and (f). ) And the output permission (OE) signal maintain the 'low' level and the write WR signal maintain the 'high' level, so that the corresponding data of the SRAM is read by the address information output from the SRAM controller.

3 is a timing diagram of a microprocessor of a memory sharing circuit using a general SRAM according to the present invention, in which the microprocessor can access the SRAM by a supplied system clock, as shown in (b) and (c). As such, when the SRAM access permission signal and the buffer enable signal are at the 'low' level, the arbitration unit receiving the 'low' level SRAM permission signal generates a data strobe recognition signal and sends the signal to the microprocessor, whereby the microprocessor generates the data strobe. In response to the recognition signal, as shown in (e), the chip select signal CE may be maintained at a low level, and the access process may be terminated only during that time.

Therefore, a data bus and an address bus, and control signals for chip selection (CE), output permission (OE), and write (WR) are provided between the microprocessor 20 and the SRAM 10, and are separated from the real-time controller 30. And a mediation section 50 for providing a data strobe acknowledgment signal to the microprocessor 20 so that the microprocessor 10 can terminate one operation cycle. The SRAM access permission signal output from the real time controller 30 may be connected to the arbitration unit 20 to be used to generate a data strobe recognition signal.

For example, the memory sharing circuit of the present invention can be applied to a memory and a peripheral circuit used for a lookup table in an asynchronous transfer type exchange. The microprocessor 20 uses the SRAM 10 as a real time controller 30. By controlling the and buffers, the header of the ATM cell input to the real-time control unit 30 is read from the corresponding address of the SRAM 10 from the index and the header of the ATM cell is converted.

As described above, the present invention has the effect of maximizing real-time transmission by providing a memory sharing circuit so that two processors share a general SRAM and access memory alternately at regular intervals.

Claims (2)

A general SRAM 10 for storing data; A microprocessor (20) for initializing and randomly accessing the SRAM (10); A real time controller 30 for accessing the SRAM 10 at regular time intervals and outputting a control signal for the microprocessor 20 to access the SRAM 10 at other times; A buffer (40) operated by the control signal to allow the microprocessor (20) to access the memory (10) without colliding with the real-time controller (30); And an arbitration unit (50) for receiving the control signal and outputting a data strobe recognition signal to terminate the access of the microprocessor (20). The apparatus of claim 1, wherein the real-time control unit (30) comprises: a timer (32) for generating a predetermined timing; An SRAM control unit 34 outputting a control signal to the SRAM 10 and reading data of the SRAM 10 during a predetermined timing generated from the timer 32; And a buffer controller 36 which outputs an enable signal to the buffer 40 and outputs an SRAM access permission signal to the arbitration unit 50 during a predetermined timing generated from the timer 32. Memory sharing circuit using general SRAM.