KR930011258A - DRAM manufacturing method with trench capacitor - Google Patents

DRAM manufacturing method with trench capacitor Download PDF

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Publication number
KR930011258A
KR930011258A KR1019910020724A KR910020724A KR930011258A KR 930011258 A KR930011258 A KR 930011258A KR 1019910020724 A KR1019910020724 A KR 1019910020724A KR 910020724 A KR910020724 A KR 910020724A KR 930011258 A KR930011258 A KR 930011258A
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KR
South Korea
Prior art keywords
film
forming
trench
oxide
interlayer insulating
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KR1019910020724A
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Korean (ko)
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KR940009631B1 (en
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김윤기
김병렬
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김광호
삼성전자 주식회사
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Priority to KR1019910020724A priority Critical patent/KR940009631B1/en
Publication of KR930011258A publication Critical patent/KR930011258A/en
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Publication of KR940009631B1 publication Critical patent/KR940009631B1/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
    • H10B12/0387—Making the trench
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
    • H10B12/0385—Making a connection between the transistor and the capacitor, e.g. buried strap

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)

Abstract

내용 없음No content

Description

트랜치 커패시터를 갖는 DRAM의 제조방법DRAM manufacturing method with trench capacitor

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제 1 도는 종래의 트랜치 커패시터 제조방법의 순서도.1 is a flow chart of a conventional trench capacitor manufacturing method.

제 2 도는 본 발명의 트랜치 커패시터를 갖는 DRAM의 제조방법의 순서도.2 is a flowchart of a method of manufacturing a DRAM having a trench capacitor of the present invention.

Claims (10)

실리콘기판상에 필드산화막을 형성한 후 게이트전극을 형성하고 소오스/드레인 불순물 영역을 이온주입에 의하여 형성하고, 층간절연막을 형성한 후 매몰 콘택(Burried Contact)을 형성하는 단계와, 상기 층간절연막을 마스크로 사용하여 트랜치가 형성될 부분의 실리콘기판을 소정의 깊이로 1차 식각한 후, 질화막을 증착하는 단계와. 상기 트랜치내의 일부와 필드 산화막위에 형성된 질화막을 포토레지스트를 이용한 사진식각 방법으로 제거하는 단계와, 그후 포토레지스트를 제거하고 질화막을 식각하여 층간절연막의 측벽과 트랜치 벽면 상에 질화막 스페이서를 형성하고, 이 질화막 스페이서와 층간절연막을 마스크로 사용하여 실리콘기판을 2차 식각하여 트랜치를 형성하고, 상기 트랜치의 표면에 측벽산화막을 형성하는 단계와, 상기 질화막 스페이서를 식각하여 제거하는 단계와, 상기 층간절연막 및 트랜치내의 측벽산화막의 표면을 따라 스토리지전극을 형성하고 상기 스토리지전극의 외면에 절연막을 형성하고, 그 상부에 플레이트 전극을 형성하는 단계로 구성됨을 특징으로 하는 트랜치 커패시터를 갖는 DRAM의 제조방법.Forming a gate oxide after forming a field oxide film on a silicon substrate, forming a source / drain impurity region by ion implantation, forming an interlayer insulating film, and forming a buried contact; and forming the interlayer insulating film. First etching the silicon substrate of the portion where the trench is to be formed to a predetermined depth using a mask, and then depositing a nitride film; Removing a portion of the nitride film formed on the trench and the field oxide film by a photolithography method using a photoresist; and then removing the photoresist and etching the nitride film to form nitride spacers on the sidewalls and trench walls of the interlayer dielectric film. Forming a trench by secondary etching a silicon substrate using a nitride spacer and an interlayer insulating film as a mask, forming a sidewall oxide film on the surface of the trench, etching and removing the nitride spacer, and removing the interlayer insulating film and Forming a storage electrode along the surface of the sidewall oxide film in the trench, forming an insulating film on the outer surface of the storage electrode, and forming a plate electrode thereon. 제 1 항에 있어서, 상기 스토리지 전극 형성이 스토리지전극과 소오스 불순물 영역이 자연접촉되는 것을 특징으로 하는 트랜치 커패시터를 갖는 DRAM의 제조방법.The method of claim 1, wherein the storage electrode is formed in natural contact between the storage electrode and a source impurity region. 제 1 항에 있어서, 상기 질화막 형성전에 전표면에 초박막의 산화막을 증착하는 단계를 도포하는 것을 특징으로 하는 트랜치 커패시터를 갖는 DRAM의 제조방법.The method of manufacturing a DRAM having a trench capacitor according to claim 1, wherein the step of depositing an ultra thin oxide film on the entire surface before forming the nitride film. 제 1 항 또는 2 항에 있어서, 상기의 질화막 스페이서 및 박막의 산화막의 식각시, 트랜치측의 소오스 불순물 영역의 측벽 노출되도록 완전히 제거함을 특징으로 하는 트랜치 커패시터를 갖는 DRAM의 제조방법.The method of manufacturing a DRAM having a trench capacitor according to claim 1 or 2, wherein the nitride spacer and the thin film oxide are etched completely so as to expose sidewalls of source impurity regions on the trench side. 제 3 항에 있어서, 상기의 박막의 산화막의 두께는 트랜치내의 산화막보다 얇게 형성됨을 특징으로 하는 트랜치 커패시터를 갖는 DRAM의 제조방법.4. The method of claim 3, wherein the thickness of the oxide film of the thin film is thinner than the oxide film in the trench. 제 1 항에 있어서, 상기 층간절연막은 700℃ 이상의 고온에서 LPCVD공정에 의하여 형성된 HTO(High Temperature Oxide)막임을 특징으로 하는 트랜치 커패시터를 갖는 DRAM의 제조방법.The method of claim 1, wherein the interlayer insulating layer is a high temperature oxide (HTO) film formed by an LPCVD process at a high temperature of 700 ° C. or higher. 제 6 항에 있어서, 상기 층간절연막은 더욱 바람직하게는 850℃의 온도에서 LPCVD공정에 의하여 형성된 HTO(High Temperature Oxide)막임을 특징으로 하는 트랜치 커패시터를 갖는 DRAM의 제조방법.7. The method of claim 6, wherein the interlayer insulating film is more preferably a high temperature oxide (HTO) film formed by an LPCVD process at a temperature of 850 占 폚. 제 1 항에 있어서, 상기 스토리지 전극은 게이트 산화막 및 트랜치내의 산화막의 표면을 따라 폴리실리콘층을 증착한 후, 폴리 실리콘층에 대한 열처리 단계를 더 포함하는 것을 특징으로 하는 트랜치 커패시터를 갖는 DRAM의 제조방법.2. The fabrication of a DRAM having a trench capacitor according to claim 1, wherein the storage electrode further comprises a step of depositing a polysilicon layer along the surfaces of the gate oxide layer and the oxide layer in the trench, and then heat treating the polysilicon layer. Way. 제 8 항에 있어서, 상기 폴리실리콘층에 대한 열처리 온도는 바람직하게는 560℃ 이상임을 특징으로하는 트랜치 커패시터를 갖는 DRAM의 제조방법.9. The method of claim 8, wherein the heat treatment temperature for the polysilicon layer is preferably 560 [deg.] C. or higher. 제 8 항에 있어서, 상기 스토리지전극은 HSG, 도우프된 폴리실리콘, 또는 폴리실리콘 형성 후 이온 주입된 폴리실리콘중 하나로 이루어지는 것을 특징으로 하는 트랜치 커패시터를 갖는 DRAM의 제조방법.10. The method of claim 8, wherein the storage electrode is made of one of HSG, doped polysilicon, or polysilicon implanted after polysilicon formation. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019910020724A 1991-11-20 1991-11-20 Manufacturing method of dram with trench capacitor KR940009631B1 (en)

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KR930011258A true KR930011258A (en) 1993-06-24
KR940009631B1 KR940009631B1 (en) 1994-10-15

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010019223A (en) * 1999-08-25 2001-03-15 오용수 Artificial stone materials and preparation thereof
KR100400633B1 (en) * 2000-08-22 2003-10-04 손명모 Preparation of high strength floor brick using the recycling glasses
KR100400634B1 (en) * 2000-08-22 2003-10-08 손명모 Preparation of high strength light weight tiles and bricks using the recycling glasses
KR100403856B1 (en) * 2000-07-31 2003-11-01 신승태 Inorganic Building Materials Using Refused Glass And Method for Manufacturing The Same

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010019223A (en) * 1999-08-25 2001-03-15 오용수 Artificial stone materials and preparation thereof
KR100403856B1 (en) * 2000-07-31 2003-11-01 신승태 Inorganic Building Materials Using Refused Glass And Method for Manufacturing The Same
KR100400633B1 (en) * 2000-08-22 2003-10-04 손명모 Preparation of high strength floor brick using the recycling glasses
KR100400634B1 (en) * 2000-08-22 2003-10-08 손명모 Preparation of high strength light weight tiles and bricks using the recycling glasses

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KR940009631B1 (en) 1994-10-15

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