KR930004047A - 이중몰딩 패키지 및 몰드 금형 - Google Patents

이중몰딩 패키지 및 몰드 금형 Download PDF

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Publication number
KR930004047A
KR930004047A KR1019910013949A KR910013949A KR930004047A KR 930004047 A KR930004047 A KR 930004047A KR 1019910013949 A KR1019910013949 A KR 1019910013949A KR 910013949 A KR910013949 A KR 910013949A KR 930004047 A KR930004047 A KR 930004047A
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KR
South Korea
Prior art keywords
mold
molding
package
double
cavity
Prior art date
Application number
KR1019910013949A
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English (en)
Other versions
KR940005711B1 (ko
Inventor
노길섭
Original Assignee
정몽헌
현대전자산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 정몽헌, 현대전자산업 주식회사 filed Critical 정몽헌
Priority to KR1019910013949A priority Critical patent/KR940005711B1/ko
Publication of KR930004047A publication Critical patent/KR930004047A/ko
Application granted granted Critical
Publication of KR940005711B1 publication Critical patent/KR940005711B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Moulds For Moulding Plastics Or The Like (AREA)
  • Injection Moulding Of Plastics Or The Like (AREA)

Abstract

내용 없음.

Description

이중몰딩 패키지 및 몰드 금형
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제5도는 리드플임을 몰딩시킨 상태의 예시사시도.
제6도는 일반적인 몰드금형의 단면도.
제7도 (가)는 종래의 프라스틱 패키지(P―DIP) 제조용 캐비티 평면도, (나)는 제7도 (가)의 A―A선 단면도.
제8도 (가)는 종래의 PLCC형 패키지 제조를 위한 캡티 블록 평면도, (나)는 제8도 (가)의 B―B선 단면도.
제9도는 본 발명에 따른 1차 몰딩 상태의 패키지 측면도.
제10도는 본 발명에 따른 2차 몰딩 상태의 패키지 측면도.
제11도 (가)는 본 발명의 1차 몰딩을 위한 캐비티의 일예를 보인 평면도, (나)는 제9도 (가)의 사시도.

Claims (5)

  1. 상면(110)이 패키지의 표면을 이루도록 하며 패키지의 크기보다 작게 리드프레임(6)의 몰딩위에 형성된 1차 몰딩물(100)과, 1차 몰딩물(100)의 상면(110)을 제외한 측면 및 하면 부위를 감싸도록 몰딩시켜 패키지를 이루도록 하는 2차 몰딩물(120)로 구성됨을 특징으로 하는 이중 몰딩 패키지.
  2. 제1항에 있어서, 1차 몰딩몰(100)의 측면은 리드프레임(6)과 접하는 부위로 갈수록 폭이 커지도록된 단부(111)가 형성됨을 특징으로 하는 이중 몰딩 패키지.
  3. 제1항에 있어서, 1차 몰딩물(100)은 크린 펌파운드이며, 2차 몰딩물(120)은 같은 계열의 에폭시수지 임을 특징으로 하는 이중 몰딩 패키지.
  4. 체이스에 캐비티가 형성된 몰드금형을 구성함에 있어서, 체이스(34)의 캐비티(33) 측면에 측면방향을 따라 형성된 에어밴트(50)를 포함함을 특징으로 하는 이중 몰딩 패키지용 몰드금형.
  5. 제4항에 있어서, 캐비티(33)의 내측면에는 수개의 단을 이룬 단부(51)가 측면을 따라 형성됨을 특징으로하는 이중몰딩 패키지용 몰드금형.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019910013949A 1991-08-13 1991-08-13 이중몰딩 패키지 및 몰드 금형 KR940005711B1 (ko)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019910013949A KR940005711B1 (ko) 1991-08-13 1991-08-13 이중몰딩 패키지 및 몰드 금형

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910013949A KR940005711B1 (ko) 1991-08-13 1991-08-13 이중몰딩 패키지 및 몰드 금형

Publications (2)

Publication Number Publication Date
KR930004047A true KR930004047A (ko) 1993-03-22
KR940005711B1 KR940005711B1 (ko) 1994-06-23

Family

ID=19318518

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910013949A KR940005711B1 (ko) 1991-08-13 1991-08-13 이중몰딩 패키지 및 몰드 금형

Country Status (1)

Country Link
KR (1) KR940005711B1 (ko)

Also Published As

Publication number Publication date
KR940005711B1 (ko) 1994-06-23

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