KR930003444B1 - 주기억 참조의 순차화 제어방식 - Google Patents

주기억 참조의 순차화 제어방식 Download PDF

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Publication number
KR930003444B1
KR930003444B1 KR1019890014644A KR890014644A KR930003444B1 KR 930003444 B1 KR930003444 B1 KR 930003444B1 KR 1019890014644 A KR1019890014644 A KR 1019890014644A KR 890014644 A KR890014644 A KR 890014644A KR 930003444 B1 KR930003444 B1 KR 930003444B1
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KR
South Korea
Prior art keywords
cpu
sequencing
cpus
notification
main memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
KR1019890014644A
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English (en)
Korean (ko)
Other versions
KR900006872A (ko
Inventor
아이찌로 이노우에
Original Assignee
후지쓰 가부시끼가이샤
야마모도 다꾸마
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 후지쓰 가부시끼가이샤, 야마모도 다꾸마 filed Critical 후지쓰 가부시끼가이샤
Publication of KR900006872A publication Critical patent/KR900006872A/ko
Application granted granted Critical
Publication of KR930003444B1 publication Critical patent/KR930003444B1/ko
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/52—Program synchronisation; Mutual exclusion, e.g. by means of semaphores

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Multi Processors (AREA)
  • Hardware Redundancy (AREA)
KR1019890014644A 1988-10-12 1989-10-12 주기억 참조의 순차화 제어방식 Expired - Fee Related KR930003444B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP63256604A JPH02103656A (ja) 1988-10-12 1988-10-12 主記憶参照の遂次化制御方式
JP63-256604 1988-10-12

Publications (2)

Publication Number Publication Date
KR900006872A KR900006872A (ko) 1990-05-09
KR930003444B1 true KR930003444B1 (ko) 1993-04-29

Family

ID=17294939

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019890014644A Expired - Fee Related KR930003444B1 (ko) 1988-10-12 1989-10-12 주기억 참조의 순차화 제어방식

Country Status (7)

Country Link
US (1) US5297267A (https=)
EP (1) EP0364226B1 (https=)
JP (1) JPH02103656A (https=)
KR (1) KR930003444B1 (https=)
AU (1) AU614190B2 (https=)
CA (1) CA2000435C (https=)
DE (1) DE68926374T2 (https=)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6108755A (en) * 1990-09-18 2000-08-22 Fujitsu Limited Asynchronous access system to a shared storage
JP3141948B2 (ja) * 1990-09-18 2001-03-07 富士通株式会社 計算機システム
FR2678400B1 (fr) * 1991-06-27 1995-08-04 Texas Instruments France Processeur de protocole destine a l'execution d'un ensemble d'instructions en un nombre reduit d'operation.
JPH06168263A (ja) * 1992-11-30 1994-06-14 Fujitsu Ltd ベクトル処理装置
US5787488A (en) * 1993-04-22 1998-07-28 Analog Devices, Inc. Multi-phase multi-access pipeline memory system
TW353732B (en) * 1994-03-31 1999-03-01 Ibm Processing system and method of operation
US5949971A (en) * 1995-10-02 1999-09-07 International Business Machines Corporation Method and system for performance monitoring through identification of frequency and length of time of execution of serialization instructions in a processing system
US5797019A (en) * 1995-10-02 1998-08-18 International Business Machines Corporation Method and system for performance monitoring time lengths of disabled interrupts in a processing system
US5691920A (en) * 1995-10-02 1997-11-25 International Business Machines Corporation Method and system for performance monitoring of dispatch unit efficiency in a processing system
US5748855A (en) * 1995-10-02 1998-05-05 Iinternational Business Machines Corporation Method and system for performance monitoring of misaligned memory accesses in a processing system
US5751945A (en) * 1995-10-02 1998-05-12 International Business Machines Corporation Method and system for performance monitoring stalls to identify pipeline bottlenecks and stalls in a processing system
US5752062A (en) * 1995-10-02 1998-05-12 International Business Machines Corporation Method and system for performance monitoring through monitoring an order of processor events during execution in a processing system
US5729726A (en) * 1995-10-02 1998-03-17 International Business Machines Corporation Method and system for performance monitoring efficiency of branch unit operation in a processing system

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4152764A (en) * 1977-03-16 1979-05-01 International Business Machines Corporation Floating-priority storage control for processors in a multi-processor system
FR2474201B1 (fr) * 1980-01-22 1986-05-16 Bull Sa Procede et dispositif pour gerer les conflits poses par des acces multiples a un meme cache d'un systeme de traitement numerique de l'information comprenant au moins deux processus possedant chacun un cache
US4587609A (en) * 1983-07-01 1986-05-06 Honeywell Information Systems Inc. Lockout operation among asynchronous accessers of a shared computer system resource
JPS6079460A (ja) * 1983-10-07 1985-05-07 Nec Corp 密結合多重演算装置における制御方式
US4745548A (en) * 1984-02-17 1988-05-17 American Telephone And Telegraph Company, At&T Bell Laboratories Decentralized bus arbitration using distributed arbiters having circuitry for latching lockout signals gated from higher priority arbiters
US4754398A (en) * 1985-06-28 1988-06-28 Cray Research, Inc. System for multiprocessor communication using local and common semaphore and information registers
US4794521A (en) * 1985-07-22 1988-12-27 Alliant Computer Systems Corporation Digital computer with cache capable of concurrently handling multiple accesses from parallel processors
US4775955A (en) * 1985-10-30 1988-10-04 International Business Machines Corporation Cache coherence mechanism based on locking
JPH07104834B2 (ja) * 1986-06-18 1995-11-13 富士通株式会社 処理装置間ロック制御システム
US4991090A (en) * 1987-05-18 1991-02-05 International Business Machines Corporation Posting out-of-sequence fetches
US4984153A (en) * 1988-04-27 1991-01-08 Unisys Corporation Storage locking control for a plurality of processors which share a common storage unit
US5043886A (en) * 1988-09-16 1991-08-27 Digital Equipment Corporation Load/store with write-intent for write-back caches
US4965717A (en) * 1988-12-09 1990-10-23 Tandem Computers Incorporated Multiple processor system having shared memory with private-write capability

Also Published As

Publication number Publication date
AU4283989A (en) 1990-07-19
DE68926374T2 (de) 1996-11-14
EP0364226B1 (en) 1996-05-01
JPH0564825B2 (https=) 1993-09-16
AU614190B2 (en) 1991-08-22
CA2000435C (en) 1996-04-09
EP0364226A3 (en) 1992-07-08
EP0364226A2 (en) 1990-04-18
KR900006872A (ko) 1990-05-09
US5297267A (en) 1994-03-22
CA2000435A1 (en) 1990-04-12
DE68926374D1 (de) 1996-06-05
JPH02103656A (ja) 1990-04-16

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