KR930001073A - Parallel printer interface circuit for serial bus - Google Patents

Parallel printer interface circuit for serial bus Download PDF

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Publication number
KR930001073A
KR930001073A KR1019910010402A KR910010402A KR930001073A KR 930001073 A KR930001073 A KR 930001073A KR 1019910010402 A KR1019910010402 A KR 1019910010402A KR 910010402 A KR910010402 A KR 910010402A KR 930001073 A KR930001073 A KR 930001073A
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KR
South Korea
Prior art keywords
data
serial bus
signal
pal
buffer
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KR1019910010402A
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Korean (ko)
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KR930008045B1 (en
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류경
Original Assignee
이헌조
주식회사 금성사
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Priority to KR1019910010402A priority Critical patent/KR930008045B1/en
Publication of KR930001073A publication Critical patent/KR930001073A/en
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Publication of KR930008045B1 publication Critical patent/KR930008045B1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)
  • Accessory Devices And Overall Control Thereof (AREA)

Abstract

내용 없음No content

Description

직렬버스용 병렬 프린터 인터페이스 회로Parallel Printer Interface Circuit for Serial Bus

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제 1 도는 종래의 프린터 인터페이스회로도.1 is a conventional printer interface circuit diagram.

제 2 도는 본 발명에 따른 직렬버스용 프린터 인터페이스회로 블록도.2 is a block diagram of a printer interface circuit for a serial bus according to the present invention.

제 3 도는 본 발명에 따른 팔(PAL1)소자의 상태도.Figure 3 is a state diagram of the arm (PAL 1 ) element according to the present invention.

제 4 도는 본 발명에 따른 팔(PAL2)소자의 상태도.4 is a state diagram of an arm (PAL 2 ) device according to the present invention.

제 5a,a' 도는 제 2 도에 따른 팔(PAL1)소자의 타이밍도.Fig. 5a, a 'or timing diagram of the arm PAL 1 element according to Fig. 2;

제 6a, b 도는 팔(PAL2)소자의 타이밍도.6a, b or timing diagram of an arm PAL 2 element.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

11 : 직렬버스 12 : 데이타버퍼11: serial bus 12: data buffer

13 : 이피롬 14 : 팔(PAL1)소자13: pyrom 14: arm (PAL 1 ) element

15 : 팔(PAL2)소자 16 : 데이타버스15: arm (PAL 2 ) device 16: data bus

17 : 데이타래치 18 : 버퍼17: data latch 18: buffer

19 : 래치 20 : 플립플롭19: latch 20: flip-flop

21 : 프린터 22 : 분주기21: printer 22: divider

Claims (4)

직렬버스(11)와 데이타 인터페이스를 위해 데이타를 버퍼링하는 데이타버퍼(12)와, 상기 직렬버스(11)의 병렬어드레스(PA)에 의해 억세스되는 이피롬(13)과, 프린터(21)측에 전송되는 데이타를 래치시키는 데이타 래치(17)와, 프린터(21)로부터 출력되는 데이타(Busy, Select,, PE)를 버퍼링하는 버퍼(18)와, 프린터(21)측에 리세트신호()를 출력하는 래치(19)와, 상기 데이타버퍼(12), 이피롬(13), 데이타래치(17), 버퍼(18) 및 래치(19)의 상호 데이타 입출력을 하는 데이타(7 :)버스(16)와, 상기 직렬버스(11)의 콘트롤신호를 디코딩하여 각부제어신호(, DIR,RD,)를 발생함과 직렬버스(11)와 인지신호()를 주고받는 팔(PAL1)소자(14)와, 상기 직렬버스(11)의 콘트롤신호를 디코딩하여 상기 프린터(21)측에 데이타스트로브신호()를 출력하는 팔(PAL2)소자(15)와, 상기 프린터(21)측의 인지신호()에 따라 직렬버스(11)측에 인터럽트신호를 발생하는 플립플롭(20)으로 구성된 것을 특징으로 하는 직렬버스용 병렬 프린터 인터페이스회로.The data buffer 12 buffering data for the serial bus 11 and the data interface; A data latch 17 for latching data to be transmitted, and data output from the printer 21 (Busy, Select, , A buffer 18 for buffering the PE, and a reset signal ( ), And the data (7 :) for mutual data input / output of the data buffer 12, the epirom 13, the data latch 17, the buffer 18, and the latch 19. Bus 16 and control signals of the serial bus 11 to decode , DIR, RD, ) And the serial bus 11 and the acknowledgment signal ( ) And a control signal of the serial bus 11 and the arm PAL 1 to exchange the data strobe signal (PAL 1 ). ) PAL 2 outputting element 15 and the recognition signal of the printer 21 side ( A parallel printer interface circuit for a serial bus, comprising a flip-flop (20) for generating an interrupt signal at the serial bus (11). 제 1 항에 있어서, 팔(PAL1)소자(14)에 인가되는 (CLK1)을 소정분주시켜 팔(PAL2)소자(15)의 클럭(CLK2)으로 인가시키는 분주기(22)를 포함시켜 구성된 것을 특징으로 하는 직렬버스용 병렬 프린터 인터페이스회로.The frequency divider (22) according to claim 1, wherein the frequency divider (22) is applied to the clock (CLK 2 ) of the arm (PAL 2 ) element 15 by predetermined division of the (CLK 1 ) applied to the arm (PAL 1 ) element 14. Parallel printer interface circuit for serial bus, characterized in that configured to include. 제 1 항에 있어서, 팔(PAL1)소자(14)는 직렬버스(11)측의 콘트롤 신호[READ, PA23, PA(1 :)]의 조건에 의해 데이타버퍼(12)의 디렉션(DIR) 선택을 한 후 버퍼(18)의 읽기신호() 또는 이피롬(13)의 인에이블()신호를액티브시키고 소정타이밍(S5)에서 인지신호 [(2 :)]를 액티브시켜 직렬버스(11)측에서 데이타를 읽어가게 하는 것을 특징으로 하는 직렬버스용 병렬 프린터 인터페이스회로.The arm PAL 1 element 14 is a control signal of the serial bus 11 side. READ, PA 23 , PA (1: After selecting the direction (DIR) of the data buffer 12 according to the condition of []], the read signal of the buffer 18 ( ) Or enable of pyrom (13) ) Or the active signal and at a predetermined timing (S 5) signal - (2 : A serial printer interface circuit for serial buses, characterized in that the data is read from the serial bus (11) side by activating)]. 제 1 항에 있어서, 팔(PAL1)소자(14)는 직렬버스(11)측의 콘트롤신호[READ, PA23, PA(1 :)]의 조건에 의해 데이타버퍼(12) 의 디렉션(DIR)선택을 한 후 데이타래치(17) 및 래치(18)의 쓰기신호(), ()를 액티브시키고, 데이타를 받았다는 인지신호[ACK(2 :)]를 발생시켜 데이타 쓰기 사이클을 마치도록 하는 것을 특징으로 하는 직렬버스용 병렬 프린터 인터페이스회로.2. The arm PAL 1 element 14 is a control signal of the serial bus 11 side. READ, PA 23 , PA (1: After selecting the direction (DIR) of the data buffer 12 according to the condition of []], the write signals of the data latch 17 and the latch 18 ( ), ( ) Is activated, and an acknowledgment signal of receiving data [ACK (2: A serial printer interface circuit for a serial bus, characterized in that to generate data) and end a data write cycle. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019910010402A 1991-06-22 1991-06-22 Interface circuit of parallel printer for a serial bus KR930008045B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019910010402A KR930008045B1 (en) 1991-06-22 1991-06-22 Interface circuit of parallel printer for a serial bus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910010402A KR930008045B1 (en) 1991-06-22 1991-06-22 Interface circuit of parallel printer for a serial bus

Publications (2)

Publication Number Publication Date
KR930001073A true KR930001073A (en) 1993-01-16
KR930008045B1 KR930008045B1 (en) 1993-08-25

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KR1019910010402A KR930008045B1 (en) 1991-06-22 1991-06-22 Interface circuit of parallel printer for a serial bus

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102176330B1 (en) 2019-06-12 2020-11-09 김상운 The dice mold structure of the long bolt for manufacture heading machine
KR20200142477A (en) 2019-06-12 2020-12-22 김상운 The dice mold structure of the long bolt for manufacture heading machine

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102176330B1 (en) 2019-06-12 2020-11-09 김상운 The dice mold structure of the long bolt for manufacture heading machine
KR20200142477A (en) 2019-06-12 2020-12-22 김상운 The dice mold structure of the long bolt for manufacture heading machine

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KR930008045B1 (en) 1993-08-25

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