KR930008045B1 - Interface circuit of parallel printer for a serial bus - Google Patents

Abstract

This device forms a parallel printer interface circuit for a serial bus and is composed of: a data buffer which buffers for the data interface of the serial bus; an EPROM which is accessed by the parallel address of the serial bus; a latch which latches data to the printer side; a printer buffer; a data bus which inputs and outputs data; a PAL which emits generating signals by decoding control signals and sends/receives perception signals; and a flip-flop which emits interrupt signals to the serial bus depending on printer perception signals.

Description

Parallel Printer Interface Circuit for Serial Bus

1 is a conventional printer interface circuit diagram.

2 is a block diagram of a printer interface circuit for a serial bus according to the present invention.

Figure 3 is a state diagram of the arm (PAL ₁ ) element according to the present invention.

4 is a state diagram of an arm (PAL ₂ ) device according to the present invention.

Fig. 5a, a 'or timing diagram of the arm PAL ₁ element according to Fig. 2;

6a, b or timing diagram of an arm PAL ₂ element.

* Explanation of symbols for main parts of the drawings

11: serial bus 12: data buffer

13: pyrom 14: arm (PAL ₁ ) element

15: arm (PAL ₂ ) device 16: data bus

17: data latch 18: buffer

19: latch 20: flip-flop

21: printer 22: divider

The present invention is to provide a parallel data transfer (Parallel Data Transfer) to a computer system using a serial bus (SBus), in particular, by implementing a low-cost high-speed interface card (Centronics) It relates to a parallel printer interface circuit for a serial bus, which is suitable for a printer of a type).

In general, the interface method of the parallel printer is configured such that the central processing unit 1 and the printer 3 are interfaced through the printer control logic 2, as shown in FIG.

The printer control logic 2 in charge of the interface between the central processing unit 1 and the printer 2 shakes hands and transmits data. Then, the central processing unit 1 keeps checking until it is ready to transmit the next character, and then transmits it after the next character transmission preparation is finished.

As described above, since the CPU 1 uses a polling method, the data transmission speed is significantly lower, the time wasted in the CPU 1, and a special chip (eg, Z8536) is used for the interface. The price is high.

An object of the present invention is to increase the data transfer speed of the central processing unit and the printer, and another purpose is to reduce the cost of the system configuration, which is a data buffer, latch, arm to interface the serial bus and parallel printer of the central processing unit. The object of the present invention is achieved by constructing a parallel bus interface circuit for a serial bus using a (PAL) circuit and an epi-ROM. This will be described in detail with reference to the accompanying drawings.

2 is a block diagram of a parallel printer interface circuit for a serial bus according to the present invention. As shown in FIG. ) And the control signal of the serial bus (11) READ, , PA ₂₃ , PA , PA ₁ ) to decode the control signal ( , DIR, , RD, PAL ₁ generating element 14) and data strobe ( PAL ₂ generating element 15, a data latch 17 for transmitting data to the printer 21, data of the printer 21 (Busy, Select, And a buffer 18 for buffering the PE, and a reset signal to the printer 21. ) And a latch signal 19 of the printer 21, The flip-flop 20 for interrupt output to the serial bus 11 and the data buffer 12, the epirom 13, the data latch 7, the buffer 18 and the latch 19 It consists of a data bus 16 for data transfer. Here, reference numeral 22 denotes a divider for generating the clock CLK ₂ of the arm PAL ₂ element 15.

Referring to the operation and effects of the present invention configured as described above are as follows.

The third turning a state diagram of the arm (PAL ₁₎ device according to the invention, the arm ₍₁ PAL) device 14 includes control signal receiving through the serial bus 11 ( READ, , PA ₂₃ , PA , PA ₁ ) to decode in synchronization with the clock (CLK = 40ns). -S ₆ ) and the initial state (S ) Is the reset signal ( = "L"), address strobe ( = "H") or select signal ( Its initial state (S) by " H " ) While outputting the direction (Direction: DIR = "H") signal and keeping the address strobe ( ), Select signal ( ) Is the active signal ( = "L") is a first state (S ₁₎ when the read signal ( ) Outputs a direction signal (DIR = "H") when active, PA ₂₃ = And ( ) = "H" enables pyrom (13) enable signal ( ) To the active signal ( = "L") to the output and the enable signal second state (S ₂₎ to the direction signal (DIR) two feet ROM (13 in the same conditions as in the first state in the next clock) ( ) And PA ₂₃ = 1, PA (1: ) = When the skid signal of the data latch 17 ( ) To the active signal ( = "L"), PA ₂₃ = 1, PA (1: ) = 1 Is the write signal of the latch 19 ) To the active signal ( ) = When it is 1, the read signal of the control buffer 18 ( ) To the active signal ( = "L") After that, in the third state S ₃ and the fourth state S ₄ , the control signals DIR, WR ₂ , ) Is output as an active signal, and in the fifth state (S ₅ ), in the sixth state (S ₆ ), DIR, ,

4 is a state diagram of an arm PAL ₂ device according to the present invention, and as shown therein, the arm device PAL ₂ is connected to a control signal from the serial bus 11. READ, , RA ₂₃ , PA (1: 9 status (SEQ) -SEQ ₈ to decode the data strobe signal ( ) Is generated and output to the printer 21, the chip select signal (PAL ₁ ) from the element (14) ) And the initial state (SEQ) by the reset signal (RESET = "H"). ), And ( = "L"), PA ₂₃ = 1, PA (1: ) = In the first state (SEQ ₁ ) when the reset signal ( The second state (SEQ ₂ ), the third state (SEQ ₃ ), the fourth state (SEQ ₄ ), and the eighth state (SEQ ₈ ) in the fifth state (SEQ ₅ ) in the active state of ″ L ”). Data strobe signal ( Generates = "L"). At this time, the operation clock CLK ₂ is a signal generated from the divider 22 and its period is 320ns.

(A) to (a ') are decoding timing diagrams of the arm PAL ₁ device according to the present invention, and FIGS. 6a and b are decoding timing charts of the arm PAL ₂ device according to the present invention. 7 states (S in synchronization with operation clock (CLK ₁ = 40ns), (CLK ₂ = 320ns) -S ₅ -SEQ ₈ ).

At power-on, information is first sent to the central processing unit (CPU) that informs the identity of the peripherals present on the serial bus (SBus) 11 from the pyromium 13 in the parallel fritter interface card. do. Accordingly, the host system recognizes the peripheral device, and when printing is desired, the host system provides a passage for data transmission between the printer 21 and the host. The data transmission path is the SBus data lines 31:24. The read and write timings for transferring this data are as shown in FIG.

First, when data is read from the epirome 13, as shown in Figs. 5 (g) to (i), the enable signal 13 of the epirome 13 ( ) And data (7: ), Acknowledgment signal [ACK (2: It operates according to the timing of)].

As shown in (b) and (c) of FIG. 5, the address strobe ( ) And select signal ( ) Is active and the read signal READ is high, PA ₂₃ = In this case, the arm PAL ₁ element 14 changes the font of the direction signal DIR of the data buffer 12 from B to A, as shown in (f), and prints the same as (g) to the pyrom 13. Able ( Activates the signal. Before the data is output to the data buffer 12, the arm PAL ₁ element 14 recognizes the acknowledgment signal [ACK (2: 2) in a fifth state (S ₅ ; at least data is accessible). )] Must be activated before the CPU can read the data. ACK (2: ) Is inactive at the next clock and sent to the 3-state on the next clock, and ACK (2: ) Is inactive Is inactive, and at the next clock Is also inactive.

When reading from the parallel port, as shown in Figs. 5 (m) to (a '), the address strobe signal ( ) And select signal ( Is activated, and the read signal READ becomes low and PA ₂₃ = 1, the arm PAL ₁ element 14 switches the direction signal DIR of the data buffer 12 from B to A and buffers it. Read signal to 18 ) Is activated as in (m).

This is the same sequence as reading the data from the pyramid 13.

In addition, when writing data to the parallel port, the timing is the same as in (j) to (k) in FIG. Wow When the signal is activated and the READ signal becomes Low and PA ₂₃ = 1, the arm PAL ₁ element 13 sets the direction signal DIR of the data buffer 12 from A to B, and latches the data. (17) and the write signal of the latch 20 ( ), ( ) Is activated with the fifth j degree, and the data [D (7: ) Is latched to the latches 17 and 19. At this time, unlike reading, acknowledgment signal that received data [ACK (2: )] Ends the write cycle.

On the other hand, the data strobe signal ( ) Is a signal necessary only when data is transmitted from the serial bus 11 side to the printer 21. The clock CLK _{1 of the} SBus is divided through the divider 22 to synchronize the signals. As the clock CLK ₂ of the arm PAL ₂ element 15, as shown in FIG. 6B, in the fifth state (SEQ ₅ ). Is output to the printer 21 side as an active low signal.

And if you keep sending data, send one character When is activated, the CPU wakes up and transmits the next character. When the data is transmitted again, the selection signal of the flip-flop 20 ( ) Is activated to inactivate the interrupt signal, thereby improving the driver performance. Here, the selection signal of the flip-flop 20 ( ) Selection signal of SBus (11) ) Is the latch value.

As described above, the present invention requires the data stored in the latch to be transmitted to the printer after receiving the acknowledgment signal, and then transmits the next data, and processes the software to perform other processing before receiving the acknowledgment signal. This parallel printer card has the advantage of high speed and can be used for all Centronics type printers.

Claims (4)

The data buffer 12 for buffering data for the serial bus 11 and the data interface, the pyrom 13 which is accessed by the parallel address PA of the serial bus 11, and the printer 21 side. Data latch 17 for latching the data to be transmitted, and data output from the printer 21 (Busy, Select, , A buffer 18 for buffering the PE, and a reset signal ( ), And the data (7 :) for mutual data input / output of the data buffer 12, the epirom 13, the data latch 17, the buffer 18, and the latch 19. Bus 16 and control signals of the serial bus 11 to decode , DIR, RD, ) And the serial bus 11 and the acknowledgment signal ( ) And a control signal of the serial bus 11 and the arm PAL ₁ to exchange the data strobe signal (PAL ₁ ). ) PAL ₂ outputting element 15 and the recognition signal of the printer 21 side ( A parallel printer interface circuit for a serial bus, comprising a flip-flop (20) for generating an interrupt signal at the serial bus (11). The frequency divider (22) according to claim 1, wherein the frequency divider (22) is applied to the clock (CLK ₂ ) of the arm (PAL ₂ ) element 15 by predetermined division of the (CLK ₁ ) applied to the arm (PAL ₁ ) element 14. Parallel printer interface circuit for serial bus, characterized in that configured to include. The arm PAL ₁ element 14 is a control signal of the serial bus 11 side. READ, PA ₂₃ , PA (1: After selecting the direction (DIR) of the data buffer 12 according to the condition of []], the read signal of the buffer 18 ( ) Or enable of pyrom (13) ) Or the active signal and at a predetermined timing (S ₅₎ signal - (2 : A serial printer interface circuit for serial buses, characterized in that the data is read from the serial bus (11) side by activating)]. 2. The arm PAL ₁ element 14 is a control signal of the serial bus 11 side. READ, PA ₂₃ , PA (1: After selecting the direction (DIR) of the data buffer 12 according to the condition of []], the write signals of the data latch 17 and the latch 18 ( ), ( ) Is activated, and an acknowledgment signal of receiving data [ACK (2: A serial printer interface circuit for a serial bus, characterized in that to generate data) and end a data write cycle.