KR960011680A - Parallel Downloading Device Using Computer - Google Patents

Parallel Downloading Device Using Computer Download PDF

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Publication number
KR960011680A
KR960011680A KR1019940022407A KR19940022407A KR960011680A KR 960011680 A KR960011680 A KR 960011680A KR 1019940022407 A KR1019940022407 A KR 1019940022407A KR 19940022407 A KR19940022407 A KR 19940022407A KR 960011680 A KR960011680 A KR 960011680A
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South Korea
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firmware
clock
control signal
unit
flop
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KR1019940022407A
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Korean (ko)
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KR0135372B1 (en
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이상도
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박성규
대우통신 주식회사
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Priority to KR1019940022407A priority Critical patent/KR0135372B1/en
Publication of KR960011680A publication Critical patent/KR960011680A/en
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G06F15/17306—Intercommunication techniques
    • G06F15/17318—Parallel communications techniques, e.g. gather, scatter, reduce, roadcast, multicast, all to all

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Software Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Information Transfer Between Computers (AREA)

Abstract

본 발명은 컴퓨터에서 개발한 콘트롤 보드에 사용되는 펌웨어를 보다 고속으로 콘트롤 보드로 다운로딩할 수 있도록 한 컴퓨터를 이용한 병렬 다운로딩 장치에 관한 것으로, 이를 위하여, 제1CPU를 갖는 컴퓨터에서 만든 펌웨어를 제2CPU를 갖는 콘트롤 보드로 다운로딩하는 장치에 있어서, 상기 제1CPU로부터의 제어 신호에 의해 전송하기 위한 상기 펌웨어의 소정 비트를 임시 저장하기 위한 버퍼부와, 상기 제1CPU로부터의 제어 신호와 D형 플립플롭부로부터의 제어 신호에 기초하여 상기 버퍼의 상기 펌웨어의 소정 비트를 상기 콘트롤 보드로 병렬로 전송하기 위하여 제1클록을 발생하는 컴퓨터 로직부와, 상기 컴퓨터 로직부로부터의 제1클록에 동기하여 상기 버퍼로부터의 상기 펌웨어의 소정 비트를 병렬로 연결된 데이타 라인을 통하여 전송하여 임시로 저장하기 위한 래치부와, 상기 컴퓨터 로직부로부터의 제1클록에 동기하여 상기 래치부에 상기 펌웨어의 소정 비트가 저장되었음을 인지시키기 위한 상기 제어 신호를 발생하는 상기 D형 플립플롭부와 상기 D형 플립플롭부로부터의 상기 제어 신호에 기초하여 상기 래치부에 저장된 상기 펌웨어의 소정 비트를 읽기 위하여, 제어 신호를 상기 제2CPU로 발생하고 제2클록을 상기 래치부(30)로 발생하며, 상기 펌웨어의 다음 소정의 비트를 상기 버퍼에 쓰기 위한 제어 신호를 발생하기 위한 상기 제2클록을 상기 D형 플리플롭부로도 발생하는 콘트롤 로드 로직부로 이루어진 컴퓨터를 이용한 병렬 다운로딩 장치를 제공함으로서, 보다 고속으로 다운로딩할 수 있도록 하기 위한 것이다.The present invention relates to a parallel downloading device using a computer that can download firmware used for a control board developed by a computer to the control board at a higher speed. To this end, a firmware made by a computer having a first CPU is provided. An apparatus for downloading to a control board having 2 CPUs, comprising: a buffer unit for temporarily storing a predetermined bit of the firmware for transmission by a control signal from the first CPU, a control signal from the first CPU, and a D-type flip A computer logic section for generating a first clock to transmit a predetermined bit of the firmware of the buffer in parallel to the control board based on a control signal from a flop section, and in synchronization with the first clock from the computer logic section Temporarily by sending a predetermined bit of the firmware from the buffer through parallel connected data lines And a D-type flip-flop unit for generating a control signal for recognizing that a predetermined bit of the firmware is stored in the latch unit in synchronization with the first clock from the computer logic unit. Generating a control signal to the second CPU and generating a second clock to the latch unit 30 to read a predetermined bit of the firmware stored in the latch unit based on the control signal from the flip-flop unit; By providing a parallel downloading apparatus using a computer comprising a control load logic section that also generates the second clock for generating a control signal for writing a next predetermined bit of firmware into the buffer, the D-type flip-flop section. This is to make it downloadable.

Description

컴퓨터를 이용한 병렬 다운로딩 장치Parallel Downloading Device Using Computer

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 본 발명의 바람직한 실시예에 따른 컴퓨터를 이용한 병렬 다운로딩 장치에 대한 블럭 구성도.1 is a block diagram of a parallel downloading apparatus using a computer according to a preferred embodiment of the present invention.

Claims (2)

제1CPU를 갖는 컴퓨터에서 만든 펌웨어를 제2CPU를 갖는 콘트롤 보드로 다운로딩하는 장치에 있어서, 상기 제1CPU로부터의 제어 신호에 의해 전송하기 위한 상기 펌웨어의 소정 비트를 임시 저장하기 위한 버퍼부와, 상기 제1CPU로부터의 제어 신호와 D형 플립플롭부로부터의 제어 신호에 기초하여 상기 버퍼의 상기 펌웨어의 소정 비트를 상기 콘트롤 보드로 병렬로 전송하기 위하여 제1클록을 발생하는 컴퓨터 로직부와, 상기 컴퓨터 로직부로부터의 제1클록에 동기하여 상기 버퍼로부터의 상기 펌웨어의 소정 비트를 병렬로 연결된 데이타 라인을 통하여 전송하여 임시로 저장하기 위한 래치부와, 상기 컴퓨터 로직부로부터의 제1클록에 동기하여 상기 래치부에 상기 펌웨어의 소정 비트가 저장되었음을 인지시키기 위한 상기 제어 신호를 발생하는 상기 D형 플립플롭부와 상기 D형 플립플롭부로부터의 상기 제어 신호에 기초하여 상기 래치부에 저장된 상기 펌웨어의 소정 비트를 읽기 위하여, 제어 신호를 상기 제2CPU로 발생하고 제2클록을 상기 래치부(30)로 발생하며, 상기 펌웨어의 다음 소정의 비트를 상기 버퍼에 쓰기 위한 제어 신호를 발생하기 위한 상기 제2클록을 상기 D형 플리플롭부로도 발생하는 콘트롤 로드 로직부로 이루어진 컴퓨터를 이용한 병렬 다운로딩 장치.An apparatus for downloading firmware made by a computer having a first CPU to a control board having a second CPU, the apparatus comprising: a buffer unit for temporarily storing a predetermined bit of the firmware for transmission by a control signal from the first CPU; A computer logic section for generating a first clock to transmit a predetermined bit of the firmware of the buffer in parallel to the control board based on a control signal from a first CPU and a control signal from a D flip-flop section; A latch unit for temporarily transmitting and temporarily storing a predetermined bit of the firmware from the buffer in parallel through a data line connected in parallel with the first clock from the logic unit, and in synchronization with the first clock from the computer logic unit Generating the control signal for recognizing that a predetermined bit of the firmware is stored in the latch unit; In order to read a predetermined bit of the firmware stored in the latch unit based on the control signal from the flip-flop unit and the D-type flip-flop unit, a control signal is generated to the second CPU and a second clock is generated to the latch unit 30. And a control load logic unit generating the second clock for generating a control signal for writing a next predetermined bit of the firmware into the buffer. . 제1항에 있어서, 상기 D형 플립플롭부는 상기 컴퓨터 로직부로부터의 상기 제1클록이 제1D형 플립플롭의 클록 단자에 인가되고 입력 단자에 하이 레벨이 인가되어 그 반전 출력이 제2플립플롭의 프리셋 단자에 인가됨으로서, 그 출력이 상기 컴퓨터 로직부와 콘트롤 보드 로직부로 발생되고, 상기 콘트롤 보드 로직부로부터의 상기 제2클록이 제2D형 플립플롭의 클록 단자에 인가되고 입력 단자에 로우 레벨이 인가되고 그 반전 출력이 제1D형 플립플롭의 클리어 단자에 인가되어 구성된 것을 특징으로 하는 컴퓨터를 이용한 병렬 다운로딩 장치.The second flip-flop of claim 1, wherein the first flip-flop unit is applied with the first clock from the computer logic unit to a clock terminal of the first type flip-flop and a high level is applied to an input terminal. By being applied to a preset terminal of the output, the output is generated to the computer logic section and the control board logic section, and the second clock from the control board logic section is applied to the clock terminal of the 2D flip-flop and is low level at the input terminal. And a reversed output thereof is applied to a clear terminal of the 1D flip-flop. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940022407A 1994-09-07 1994-09-07 Parallel Downloading Device Using Computer KR0135372B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940022407A KR0135372B1 (en) 1994-09-07 1994-09-07 Parallel Downloading Device Using Computer

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Application Number Priority Date Filing Date Title
KR1019940022407A KR0135372B1 (en) 1994-09-07 1994-09-07 Parallel Downloading Device Using Computer

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KR960011680A true KR960011680A (en) 1996-04-20
KR0135372B1 KR0135372B1 (en) 1998-06-15

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