KR920022550A - CMOS manufacturing method using trench - Google Patents

CMOS manufacturing method using trench Download PDF

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Publication number
KR920022550A
KR920022550A KR1019910007704A KR910007704A KR920022550A KR 920022550 A KR920022550 A KR 920022550A KR 1019910007704 A KR1019910007704 A KR 1019910007704A KR 910007704 A KR910007704 A KR 910007704A KR 920022550 A KR920022550 A KR 920022550A
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KR
South Korea
Prior art keywords
trench
polysilicon
gate
oxide film
forming
Prior art date
Application number
KR1019910007704A
Other languages
Korean (ko)
Other versions
KR940009365B1 (en
Inventor
김성진
장성진
Original Assignee
문정환
금성일렉트론 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 문정환, 금성일렉트론 주식회사 filed Critical 문정환
Priority to KR1019910007704A priority Critical patent/KR940009365B1/en
Publication of KR920022550A publication Critical patent/KR920022550A/en
Application granted granted Critical
Publication of KR940009365B1 publication Critical patent/KR940009365B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

내용 없음.No content.

Description

트랜치를 이용한 CMOS 제조방법CMOS manufacturing method using trench

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도 (a)-(c)는 본 발명에 따른 트랜치를 이용한 CMOS의 제조공정도이다.2 (a)-(c) are manufacturing process diagrams of CMOS using trenches according to the present invention.

Claims (1)

제1도전형의 반도체 기판의 일정부분에 위쪽 트랜치가 아래쪽 트랜치 보다 넓은 일체형의 이중 트랜치를 형성하고 상기 아래쪽 트랜치를 절연용 산화막으로 메운후 상기 이중 트랜치의 중앙을 중심으로 일측에는 제1도전형의 웰을, 다른 일측에는 상기 제1도전형과 반대도전형인 제2도전형의 웰을 각각 형성하고 상기 각각의 웰의 위쪽 트랜치의 밑면과 위쪽 모서리 부분에 소오스 및 드레인 영역을 형성하는 공정과, 전면에 게이트 산화막과 폴리실리콘을 차레로 도포하고 상기 폴리실리콘을 등방성 식각하여 측벽 형성의 게이트를 만든후 전면에 제1산화막을 도포하고 상기 게이트상에 도포된 상기 산화막 사이의 범위로 제한해서 상기 위쪽 트랜치의 밑면을 노출시키고 그위에 노드폴리실리콘을 도포하는 공정과, 상기 노드폴리실리콘상에 제2산화막을 형성하고 상기 게이트상의 제1산화막의 일부를 식각한후 상기 위쪽 트랜치를 폴리실리콘으로 메우고 배선을 실시하는 공정으로 이루어진 트랜치를 이용한 CMOS 제조방법.The upper trench is formed in a predetermined portion of the first conductive semiconductor substrate wider than the lower trench, an integral double trench is formed, and the lower trench is filled with an insulating oxide film, and then the center of the double trench is formed on one side of the first conductive type. Forming a well on the other side, and forming a well of a second conductive type opposite to the first conductive type and forming source and drain regions on the bottom and top corners of the upper trench of each well; Applying a gate oxide film and polysilicon on the entire surface, and isotropically etching the polysilicon to form a gate having a sidewall, and then applying a first oxide on the front surface and limiting the range between the oxide films applied on the gate Exposing the bottom surface of the trench and applying nodal polysilicon thereon; and a second oxide film on the nodal polysilicon Forming a portion of the first oxide film on the gate and filling the upper trench with polysilicon; ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019910007704A 1991-05-13 1991-05-13 Cmos manufacturing method using trench KR940009365B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019910007704A KR940009365B1 (en) 1991-05-13 1991-05-13 Cmos manufacturing method using trench

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910007704A KR940009365B1 (en) 1991-05-13 1991-05-13 Cmos manufacturing method using trench

Publications (2)

Publication Number Publication Date
KR920022550A true KR920022550A (en) 1992-12-19
KR940009365B1 KR940009365B1 (en) 1994-10-07

Family

ID=19314366

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910007704A KR940009365B1 (en) 1991-05-13 1991-05-13 Cmos manufacturing method using trench

Country Status (1)

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KR (1) KR940009365B1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6583060B2 (en) 2001-07-13 2003-06-24 Micron Technology, Inc. Dual depth trench isolation

Also Published As

Publication number Publication date
KR940009365B1 (en) 1994-10-07

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