KR920020700A - 반도체 칩의 어라이먼트 방법 및 레이저 리페어용 타켓이 형성된 반도체 칩 - Google Patents

반도체 칩의 어라이먼트 방법 및 레이저 리페어용 타켓이 형성된 반도체 칩 Download PDF

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Publication number
KR920020700A
KR920020700A KR1019910005891A KR910005891A KR920020700A KR 920020700 A KR920020700 A KR 920020700A KR 1019910005891 A KR1019910005891 A KR 1019910005891A KR 910005891 A KR910005891 A KR 910005891A KR 920020700 A KR920020700 A KR 920020700A
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South Korea
Prior art keywords
semiconductor chip
target
alignment
laser repair
basic
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Application number
KR1019910005891A
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English (en)
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KR940000910B1 (ko
Inventor
한병율
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문정환
금성일렉트론 주식회사
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Application filed by 문정환, 금성일렉트론 주식회사 filed Critical 문정환
Priority to KR1019910005891A priority Critical patent/KR940000910B1/ko
Priority to US07/858,723 priority patent/US5414519A/en
Priority to DE4210774A priority patent/DE4210774B4/de
Priority to TW081102553A priority patent/TW232744B/zh
Priority to JP8879292A priority patent/JP2802561B2/ja
Publication of KR920020700A publication Critical patent/KR920020700A/ko
Application granted granted Critical
Publication of KR940000910B1 publication Critical patent/KR940000910B1/ko

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K13/00—Apparatus or processes specially adapted for manufacturing or adjusting assemblages of electric components
    • H05K13/04—Mounting of components, e.g. of leadless components
    • H05K13/0486—Replacement and removal of components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
    • H01L21/681—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment using optical controlling means
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K13/00—Apparatus or processes specially adapted for manufacturing or adjusting assemblages of electric components
    • H05K13/0015—Orientation; Alignment; Positioning
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/5442—Marks applied to semiconductor devices or parts comprising non digital, non alphanumeric information, e.g. symbols
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
    • H01L2223/5448—Located on chip prior to dicing and remaining on chip after dicing

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Lasers (AREA)
  • Lasers (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Laser Beam Processing (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)

Abstract

내용 없음

Description

반도체 칩의 어라이먼트 방법 및 레이저 리페어용 타켓이 형성된 반도체 칩
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제3도 및 제4도의 (a) 내지 (d)는 본 발명에 의한 레이저 리페어용 타켓의 실시형태를 보인 것으로, 제3도의 (a) 내지 (d)는 X스캔용 기본타켓의 평면도.
제4도의 (a) 내지 (d)는 Y스캔용 기본타켓의 평면도.
제5도의 (a) 내지 (b)는 본 발명에 의한 레이저용 타켓의 실시형태를 보인 것으로, (a)는 X-어라이먼트의 옵셋값을 구하기 위한 막대타켓의 평면도, (b)는 Y-어라이먼트의 옵셋값을 구하기 위한 막대타켓의 평면도.

Claims (4)

  1. 반도체 칩의 어라이먼트 방법에 있어서, 삼각형 모양의 기본타켓(10)에 X 또는 Y스캔을 실시하여, 그 기본타켓(10)의 중심 좌표 (X0)(Y0)와 실제 스캔시의 X, Y좌표 차이로 Xoffset값과, Yoffest값을 구한후, X-어라이먼트 및 Y-어라이먼트를 동시에 수행하도록함을 특징으로 하는 반도체 칩의 어라이먼트방법.
  2. 통상적인 반도체 칩에 있어서, 각 모서리 부위에 포커스, X-어라이먼트, Y-어라이먼트시에 사용되는 삼각형 모양의 X, Y스캔 기본타켓(10)(20)과, 씨타-어라이먼트시에 사용되는 막대타켓(30)(40)이 선택적으로 형성된 것임을 특징으로 하는 레이저 리페어용 타켓이 형성된 반도체 칩.
  3. 제2항에 있어서, 상기 X, Y스캔 기본타켓(11)(12)(13)(14),(21)(22)(23) (24)중 적어도 1개가 형성되고, 상기 막대타켓(30)(40)중 적어도 개가 형성된 것임을 특징으로 하는 레이저 리페어용 타켓이 형성된 반도체 칩.
  4. 제2항 또는 제3항에 있어서, 상기 기본타켓(11)(12)(13)(14),(21)(22)(23)(24)이 직각 이등변 삼각형인 것을 특징으로 하는 레이저 리페어용 타켓이 형성된 반도체 칩.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019910005891A 1991-04-12 1991-04-12 반도체 칩의 얼라인먼트 방법 및 레이저 리페이어용 타겟이 형성된 반도체 칩 KR940000910B1 (ko)

Priority Applications (5)

Application Number Priority Date Filing Date Title
KR1019910005891A KR940000910B1 (ko) 1991-04-12 1991-04-12 반도체 칩의 얼라인먼트 방법 및 레이저 리페이어용 타겟이 형성된 반도체 칩
US07/858,723 US5414519A (en) 1991-04-12 1992-03-27 Method for aligning a semiconductor chip to be repaired with a repair system and a laser repair target used therefor
DE4210774A DE4210774B4 (de) 1991-04-12 1992-04-01 Verfahren zum Ausrichten eines Halbleiterchips, der mit Hilfe eines Reparatursystems repariert werden soll, sowie Laser-Reparaturtarget zur Verwendung für dieses Verfahren
TW081102553A TW232744B (ko) 1991-04-12 1992-04-02
JP8879292A JP2802561B2 (ja) 1991-04-12 1992-04-09 半導体チップのアライメント方法およびレーザ修理用ターゲット

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910005891A KR940000910B1 (ko) 1991-04-12 1991-04-12 반도체 칩의 얼라인먼트 방법 및 레이저 리페이어용 타겟이 형성된 반도체 칩

Publications (2)

Publication Number Publication Date
KR920020700A true KR920020700A (ko) 1992-11-21
KR940000910B1 KR940000910B1 (ko) 1994-02-04

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KR1019910005891A KR940000910B1 (ko) 1991-04-12 1991-04-12 반도체 칩의 얼라인먼트 방법 및 레이저 리페이어용 타겟이 형성된 반도체 칩

Country Status (5)

Country Link
US (1) US5414519A (ko)
JP (1) JP2802561B2 (ko)
KR (1) KR940000910B1 (ko)
DE (1) DE4210774B4 (ko)
TW (1) TW232744B (ko)

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Also Published As

Publication number Publication date
TW232744B (ko) 1994-10-21
KR940000910B1 (ko) 1994-02-04
US5414519A (en) 1995-05-09
DE4210774A1 (de) 1992-10-15
JP2802561B2 (ja) 1998-09-24
DE4210774B4 (de) 2007-06-28
JPH05109873A (ja) 1993-04-30

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