KR920013699A - Etching Method of Polysilicon Using Selective Oxidation - Google Patents

Etching Method of Polysilicon Using Selective Oxidation Download PDF

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Publication number
KR920013699A
KR920013699A KR1019900020945A KR900020945A KR920013699A KR 920013699 A KR920013699 A KR 920013699A KR 1019900020945 A KR1019900020945 A KR 1019900020945A KR 900020945 A KR900020945 A KR 900020945A KR 920013699 A KR920013699 A KR 920013699A
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KR
South Korea
Prior art keywords
polysilicon
oxide film
selective oxidation
etching method
doped
Prior art date
Application number
KR1019900020945A
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Korean (ko)
Other versions
KR0161844B1 (en
Inventor
김대병
김은갑
Original Assignee
문정환
금성일렉트론 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 문정환, 금성일렉트론 주식회사 filed Critical 문정환
Priority to KR1019900020945A priority Critical patent/KR0161844B1/en
Publication of KR920013699A publication Critical patent/KR920013699A/en
Application granted granted Critical
Publication of KR0161844B1 publication Critical patent/KR0161844B1/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Drying Of Semiconductors (AREA)
  • Semiconductor Memories (AREA)

Abstract

내용 없음No content

Description

선택적 산화를 이용한 폴리실리콘의 식각방법Etching Method of Polysilicon Using Selective Oxidation

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제4도는 본 발명의 공정 단면도.4 is a cross-sectional view of the process of the present invention.

Claims (1)

기판위에 필드산화막을 형성하고 그 위에 n+가 도핑된 폴리실리콘과 n+가 도핑안된 폴리실리콘을 형성하는 공정과, 상기 n+가 도핑된 폴리실리콘 위에 H2/O2기체분위기에서 산화막을 형성하여 n+가 도핑안된 폴리실리콘위에는 얇은 산화막이 형성되게 하는 공정과, P/R을 사용하여 정렬 및 노광후 n+가 도핑되지 않은 폴리실리콘 위의 산화막을 식각하는 공정과, 상기 n+가 도핑안된 폴리실리콘만 1/2식각하는 공정과, 상기 n+가 도핑된 폴리실리콘 위의 산화막을 식각하는 공정과, 상기 P/R을 마스크로하여 두개의 폴리실리콘을 식각하여 선폭L1과 L2가 같게하는 공정을 차례로 실시함을 특징으로 하는 선택적 산화를 이용한 폴리실리콘의 식각방법.Forming a field oxide film on the substrate and forming n + doped polysilicon and n + doped polysilicon on the substrate, and forming an oxide film in an H 2 / O 2 gas atmosphere on the n + doped polysilicon. the n + doped untested polysilicon on top of a thin oxide film process, and P / R by using the then aligned and exposed n + a step, the n + doping of etching the oxide layer above the undoped polysilicon to be formed A half-etched polysilicon only; a step of etching an oxide film on the n + -doped polysilicon; and two polysilicones etched using the P / R as a mask, the line widths L 1 and L 2 Etching method of polysilicon using the selective oxidation, characterized in that to perform the same step in order. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019900020945A 1990-12-18 1990-12-18 Etching method for poly silicon with selective oxidation KR0161844B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019900020945A KR0161844B1 (en) 1990-12-18 1990-12-18 Etching method for poly silicon with selective oxidation

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019900020945A KR0161844B1 (en) 1990-12-18 1990-12-18 Etching method for poly silicon with selective oxidation

Publications (2)

Publication Number Publication Date
KR920013699A true KR920013699A (en) 1992-07-29
KR0161844B1 KR0161844B1 (en) 1998-12-01

Family

ID=19307789

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019900020945A KR0161844B1 (en) 1990-12-18 1990-12-18 Etching method for poly silicon with selective oxidation

Country Status (1)

Country Link
KR (1) KR0161844B1 (en)

Also Published As

Publication number Publication date
KR0161844B1 (en) 1998-12-01

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