KR920013103A - 3-terminal read / 2-terminal write register Specific register zero value read circuit of file - Google Patents

3-terminal read / 2-terminal write register Specific register zero value read circuit of file Download PDF

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Publication number
KR920013103A
KR920013103A KR1019900021835A KR900021835A KR920013103A KR 920013103 A KR920013103 A KR 920013103A KR 1019900021835 A KR1019900021835 A KR 1019900021835A KR 900021835 A KR900021835 A KR 900021835A KR 920013103 A KR920013103 A KR 920013103A
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KR
South Korea
Prior art keywords
terminal
register
file
read
zero value
Prior art date
Application number
KR1019900021835A
Other languages
Korean (ko)
Other versions
KR930007043B1 (en
Inventor
박성배
김상범
함경수
Original Assignee
경상현
재단법인 한국전자통신연구소
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Application filed by 경상현, 재단법인 한국전자통신연구소 filed Critical 경상현
Priority to KR1019900021835A priority Critical patent/KR930007043B1/en
Publication of KR920013103A publication Critical patent/KR920013103A/en
Application granted granted Critical
Publication of KR930007043B1 publication Critical patent/KR930007043B1/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30141—Implementation provisions of register files, e.g. ports
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30029—Logical and Boolean instructions, e.g. XOR, NOT

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)

Abstract

내용 없음No content

Description

3단자 읽기/2단자 쓰기 레지스터 화일의 특정레지스터 제로값 읽기회로3-terminal read / 2-terminal write register Specific register zero value read circuit of file

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명의 회로도.1 is a circuit diagram of the present invention.

Claims (1)

레지스터 화일에서, 레지스터 화일(1)의 입력단(A)(B)(C)로 각각 입력되는 5비트씩의 단자A읽기용 어드레스신호(RD-A), 단자B읽기용 어드레스 신호(RD-B), 단자C읽이용 어드레스 신호(RD-C)는 각각 NOR게이트 (N1)(N2)(N3)를 거치고 인버터(I4,I5),(I6,I7),(I8,I9)를 경유하여 NOR게이트 (N4)(N5)(N6)의 타측으로 인가되도록 하여 항상 특정레지스터(R0)를 선택할때 레지스터 화일(I0의 출력(A),(B),(C)로 상수값 0이 출력되도록 구성한 3단자 읽기/2단자 쓰기 레지스터 화일의 특정레지스터 제로값 읽기회로.In the register file, a 5-bit terminal A read address signal RD-A and a 5-bit terminal B read address signal RD-B input to the input terminals A, B and C of the register file 1, respectively. ), And the terminal C read address signal RD-C passes through the NOR gates N1, N2, and N3, respectively, and passes NOR through the inverters I4, I5, I6, I7, and I8, I9. It is configured to be applied to the other side of gate (N4) (N5) (N6) so that constant value 0 is output to register file (I) (A), (B), (C) when selecting specific register (R0). 3-terminal read / 2-terminal write register A zero register reading circuit for a specific register in the file. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019900021835A 1990-12-26 1990-12-26 Zero checking circuit for register file KR930007043B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019900021835A KR930007043B1 (en) 1990-12-26 1990-12-26 Zero checking circuit for register file

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019900021835A KR930007043B1 (en) 1990-12-26 1990-12-26 Zero checking circuit for register file

Publications (2)

Publication Number Publication Date
KR920013103A true KR920013103A (en) 1992-07-28
KR930007043B1 KR930007043B1 (en) 1993-07-26

Family

ID=19308508

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019900021835A KR930007043B1 (en) 1990-12-26 1990-12-26 Zero checking circuit for register file

Country Status (1)

Country Link
KR (1) KR930007043B1 (en)

Also Published As

Publication number Publication date
KR930007043B1 (en) 1993-07-26

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