KR900010554A - Congestion Monitoring Circuit of Microprocessor - Google Patents

Congestion Monitoring Circuit of Microprocessor Download PDF

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Publication number
KR900010554A
KR900010554A KR1019880017791A KR880017791A KR900010554A KR 900010554 A KR900010554 A KR 900010554A KR 1019880017791 A KR1019880017791 A KR 1019880017791A KR 880017791 A KR880017791 A KR 880017791A KR 900010554 A KR900010554 A KR 900010554A
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KR
South Korea
Prior art keywords
circuit
microprocessor
data holding
cpu
holding circuit
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Application number
KR1019880017791A
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Korean (ko)
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KR920007509B1 (en
Inventor
박상규
Original Assignee
유인영
대한전선 주식회사
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Priority to KR1019880017791A priority Critical patent/KR920007509B1/en
Publication of KR900010554A publication Critical patent/KR900010554A/en
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Publication of KR920007509B1 publication Critical patent/KR920007509B1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Debugging And Monitoring (AREA)

Abstract

내용 없음No content

Description

마이크로 프로세서의 폭주감시 회로Congestion Monitoring Circuit of Microprocessor

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제3도는 본 발명의 마이크로 프로세서 감시회로의 블록도, 제4도는 본 발명의 마이크로 프로세서 감시회로도, 제5도는 본 발명의 실시예의 상세한 회로도.3 is a block diagram of a microprocessor supervisory circuit of the present invention, FIG. 4 is a microprocessor supervisory circuit diagram of the present invention, and FIG. 5 is a detailed circuit diagram of an embodiment of the present invention.

Claims (3)

마이크로 프로세서의 오류를 검출하고자 한 것에 있어서; 프로세서(CPU)의 어드레스 버스를 거쳐 어드레스 디코더(AD)에 입력시켜 라이트 신호를 데이타 유지 회로(LE)와 순서발생기(SG)에 입력시키고, 프로세서(CPU)의 데이타 버스는 데이타 유지회로(LE)에 입력시켜서, 상기 순서발생기(SG)의 출력과 데이타 유지회로(LE)출력을 비교하는 비교회로(CP)를 통해 프로세서(CPU)를 리세트 시킬 수 있도록 구성한 것을 특징으로 하는 마이크로 프로세서의 폭주감시회로.Attempting to detect an error of the microprocessor; The write signal is input to the data holding circuit LE and the sequence generator SG via the address bus of the processor CPU, and the data bus of the processor CPU is the data holding circuit LE. Condensation monitoring of a microprocessor characterized in that the processor (CPU) can be reset through a comparison circuit (CP) comparing the output of the sequence generator (SG) with the output of the data holding circuit (LE). Circuit. 제1항에 있어서, 프로세서(CPU)의 데이타를 유지시켜 출력하는 데이타 유지회로(LE)와, 프로세서(CPU)의 어드레서 신호로 데이터 디코더(AD)를 거쳐 데이타유지회로(LE)에 기록하고, 카운팅하도록한 순서발생기(SG)를 구비하여서 에러를 검출할 수 있도록 구성된 것을 특징으로 하는 마이크로 프로세서의 폭주감시회로.The data holding circuit (LE) of claim 1, wherein the data holding circuit (LE) for holding and outputting data of the processor (CPU) and the address signal of the processor (CPU) are written to the data holding circuit (LE) via the data decoder (AD). And a sequence generator (SG) configured to count, so as to detect an error, the congestion monitoring circuit of the microprocessor. 제2항에 있어서, 순서발생기(SG)와 데이타 유지회로(LE)에 출력되는 신호를 입력신호(An)(Bn)로 비교하여 다를때 리세트 신호를 출력하도록 한 비교회로(CP)를 구비한 것을 특징으로 하는 마이크로 프로세서의 폭주감시회로.3. A comparison circuit (CP) according to claim 2, further comprising a comparison circuit (CP) for comparing a signal output to the sequence generator (SG) and the data holding circuit (LE) with an input signal (An) (Bn) and outputting a reset signal when the signal is different. A congestion monitoring circuit of a microprocessor, characterized in that. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019880017791A 1988-12-29 1988-12-29 Micro-processor overrun supervising circuit KR920007509B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019880017791A KR920007509B1 (en) 1988-12-29 1988-12-29 Micro-processor overrun supervising circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019880017791A KR920007509B1 (en) 1988-12-29 1988-12-29 Micro-processor overrun supervising circuit

Publications (2)

Publication Number Publication Date
KR900010554A true KR900010554A (en) 1990-07-07
KR920007509B1 KR920007509B1 (en) 1992-09-04

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019880017791A KR920007509B1 (en) 1988-12-29 1988-12-29 Micro-processor overrun supervising circuit

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KR (1) KR920007509B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100487407B1 (en) * 1998-02-26 2005-06-16 엘에스산전 주식회사 Digital output failsafe circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100487407B1 (en) * 1998-02-26 2005-06-16 엘에스산전 주식회사 Digital output failsafe circuit

Also Published As

Publication number Publication date
KR920007509B1 (en) 1992-09-04

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