KR920010066B1 - Method of producing a defined arsenic doping in silicon semiconductor substrates - Google Patents

Method of producing a defined arsenic doping in silicon semiconductor substrates

Info

Publication number
KR920010066B1
KR920010066B1 KR8714106A KR870014106A KR920010066B1 KR 920010066 B1 KR920010066 B1 KR 920010066B1 KR 8714106 A KR8714106 A KR 8714106A KR 870014106 A KR870014106 A KR 870014106A KR 920010066 B1 KR920010066 B1 KR 920010066B1
Authority
KR
South Korea
Prior art keywords
producing
glass layer
silicon semiconductor
arsenic
doping
Prior art date
Application number
KR8714106A
Other languages
English (en)
Other versions
KR880008416A (ko
Inventor
Helmuth Treichel
Frank S Becker
Original Assignee
Siemens Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Ag filed Critical Siemens Ag
Publication of KR880008416A publication Critical patent/KR880008416A/ko
Application granted granted Critical
Publication of KR920010066B1 publication Critical patent/KR920010066B1/ko

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
    • H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
    • H01L21/02214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and oxygen
    • H01L21/02216—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound comprising silicon and oxygen the compound being a molecule comprising at least one silicon-oxygen bond and the compound having hydrogen or an organic group attached to the silicon or oxygen, e.g. a siloxane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
    • H01L21/2255—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer comprising oxides only, e.g. P2O5, PSG, H3BO3, doped oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/31604—Deposition from a gas or vapour
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Chemical Vapour Deposition (AREA)
  • Glass Compositions (AREA)
  • Semiconductor Memories (AREA)
  • Element Separation (AREA)
  • Thin Film Transistor (AREA)
  • Silicon Compounds (AREA)
  • Formation Of Insulating Films (AREA)
KR8714106A 1986-12-11 1987-12-10 Method of producing a defined arsenic doping in silicon semiconductor substrates KR920010066B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE3642412.9 1986-12-11
DE3642412 1986-12-11

Publications (2)

Publication Number Publication Date
KR880008416A KR880008416A (ko) 1988-08-31
KR920010066B1 true KR920010066B1 (en) 1992-11-13

Family

ID=6316013

Family Applications (1)

Application Number Title Priority Date Filing Date
KR8714106A KR920010066B1 (en) 1986-12-11 1987-12-10 Method of producing a defined arsenic doping in silicon semiconductor substrates

Country Status (7)

Country Link
US (1) US4755486A (ko)
EP (1) EP0271072B1 (ko)
JP (1) JPS63160326A (ko)
KR (1) KR920010066B1 (ko)
AT (1) ATE69124T1 (ko)
DE (1) DE3774246D1 (ko)
HK (1) HK103793A (ko)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01287956A (ja) * 1987-07-10 1989-11-20 Toshiba Corp 半導体記憶装置およびその製造方法
KR920000708B1 (ko) * 1988-07-22 1992-01-20 현대전자산업 주식회사 포토레지스트 에치백 기술을 이용한 트렌치 캐패시터 형성방법
KR0131605B1 (ko) * 1989-03-23 1998-04-15 고스기 노부미쓰 반도체장치의 제조방법
DE4013929C2 (de) * 1989-05-02 1995-12-07 Toshiba Kawasaki Kk Verfahren zum Einbringen von Störstoffen in eine Halbleitermaterial-Schicht beim Herstellen eines Halbleiterbauelements und Anwendung des Verfahrens
US5116778A (en) * 1990-02-05 1992-05-26 Advanced Micro Devices, Inc. Dopant sources for cmos device
EP0491975A1 (de) * 1990-12-21 1992-07-01 Siemens Aktiengesellschaft Verfahren zur Erzeugung einer definierten Arsendotierung in geätzten Gräben in Silizium-Halbleitersubstraten
DE59010916D1 (de) * 1990-12-21 2000-11-30 Siemens Ag Verfahren zur Herstellung einer mit Arsen dotierten glatten polykristallinen Siliziumschicht für höchstintegrierte Schaltungen
US5308790A (en) * 1992-10-16 1994-05-03 Ncr Corporation Selective sidewall diffusion process using doped SOG
TW304293B (en) * 1996-11-18 1997-05-01 United Microelectronics Corp Manufacturing method for shallow trench isolation
US6030445A (en) * 1997-05-15 2000-02-29 Advanced Delivery & Chemical Systems, Ltd. Multi-component mixtures for manufacturing of in situ doped borophosphosilicate
AT2173U1 (de) * 1997-06-19 1998-05-25 Austria Mikrosysteme Int Verfahren zur herstellung von begrenzten, dotierten teilgebieten in einem substratmaterial aus monokristallinem silizium
DE19735399C2 (de) * 1997-08-14 2002-01-17 Infineon Technologies Ag Gasleitungssystem für einen Prozeßreaktor, insbesondere Vertikalofen, zur Behandlung von Wafern und Verfahren zur Behandlung von Wafern in einem Prozeßreaktor
US6107135A (en) * 1998-02-11 2000-08-22 Kabushiki Kaisha Toshiba Method of making a semiconductor memory device having a buried plate electrode
US6099902A (en) * 1998-07-18 2000-08-08 United Silicon Incorporated Method of determining a time to clean a low pressure chemical vapor deposition (LPCVD) system
TW419779B (en) * 1998-07-31 2001-01-21 Ibm An improved method of forming an arsenic silicon glass film onto a silicon structure
EP0977249A3 (en) * 1998-07-31 2003-07-16 International Business Machines Corporation An improved method of forming an arsenic silicon glass film onto a silicon structure
DE19939589B4 (de) * 1999-08-20 2004-08-12 Infineon Technologies Ag Verfahren zur Herstellung eines Grabens mit vergrabener Platte

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3798081A (en) * 1972-02-14 1974-03-19 Ibm Method for diffusing as into silicon from a solid phase
EP0141496A1 (en) * 1983-08-31 1985-05-15 Morton Thiokol, Inc. Process for deposition silicon dioxide containing dopant onto a substrate
DD236619C2 (de) * 1985-04-24 1990-10-24 Halbleiterwerk Veb Verfahren zur abscheidung von arsen- oder antimonsilikatglas-quellschichten
EP0204182B1 (de) * 1985-05-22 1991-06-05 Siemens Aktiengesellschaft Verfahren zum Herstellen von mit Bor und Phosphor dotierten Siliziumoxid-Schichten für integrierte Halbleiterschaltungen
US4693781A (en) * 1986-06-26 1987-09-15 Motorola, Inc. Trench formation process

Also Published As

Publication number Publication date
DE3774246D1 (de) 1991-12-05
US4755486A (en) 1988-07-05
KR880008416A (ko) 1988-08-31
EP0271072A1 (de) 1988-06-15
EP0271072B1 (de) 1991-10-30
JPS63160326A (ja) 1988-07-04
ATE69124T1 (de) 1991-11-15
HK103793A (en) 1993-10-08

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