KR920008762A - Bit Line Selection Circuit of Gallium Arsenide S-RAM - Google Patents

Bit Line Selection Circuit of Gallium Arsenide S-RAM Download PDF

Info

Publication number
KR920008762A
KR920008762A KR1019900016021A KR900016021A KR920008762A KR 920008762 A KR920008762 A KR 920008762A KR 1019900016021 A KR1019900016021 A KR 1019900016021A KR 900016021 A KR900016021 A KR 900016021A KR 920008762 A KR920008762 A KR 920008762A
Authority
KR
South Korea
Prior art keywords
output
input
gates
bits
bit line
Prior art date
Application number
KR1019900016021A
Other languages
Korean (ko)
Other versions
KR930006632B1 (en
Inventor
이창석
윤광준
박형무
성낙선
Original Assignee
경상현
재단법인 한국전자통신연구소
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 경상현, 재단법인 한국전자통신연구소 filed Critical 경상현
Priority to KR1019900016021A priority Critical patent/KR930006632B1/en
Publication of KR920008762A publication Critical patent/KR920008762A/en
Application granted granted Critical
Publication of KR930006632B1 publication Critical patent/KR930006632B1/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction

Abstract

내용 없음.No content.

Description

갈륨비소 S램의 비트라인 선택회로Bit Line Selection Circuit of Gallium Arsenide S-RAM

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 일반적인 S램의 읽기동작시 신호의 흐름상태를 나타낸 블럭도.1 is a block diagram showing a signal flow state during a normal S-RAM read operation.

제2도는 일반적인 S램의 센스앰프와 출력 버퍼사이이의 연결상태를 개략적으로 나타낸 블럭도.2 is a block diagram schematically illustrating a connection state between a sense amplifier and an output buffer of a general S-RAM.

제3도는 본 발명의 S램의 비트라인 선택회로의 일실시예에 따른 구성을 나타낸 블럭도.3 is a block diagram showing a configuration of an embodiment of a bit line selection circuit of an S-RAM according to the present invention.

제4도는 본 발명의 S램의 비트라인 선택회로의 다른 실시예에 따른 구성을 나타낸 블럭도.4 is a block diagram showing a configuration according to another embodiment of the bit line selection circuit of the S-RAM of the present invention.

제5도는 본 발명의 비트라인 선택회로에서의 지연시간과 종래의 비트라인 선택회로에서의 지연시간을 비교하여 나타낸 그래프.5 is a graph showing a comparison between the delay time in the bit line selection circuit of the present invention and the delay time in the conventional bit line selection circuit.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

JDa~J71a,JDb~J71b,J100a~J171a,J100b~j171b : FETJDa to J71a, JDb to J71b, J100a to J171a, J100b to j171b: FET

N0~N71,N100~N171 : NOR게이트 또는 어드레스 디코더N0 ~ N71, N100 ~ N171: NOR gate or address decoder

S0~S63,S100~S107 : 센스앰프S0 ~ S63, S100 ~ S107: Sense Amplifier

Claims (3)

X쪽과 Y쪽으로 64×64개의 메모리 셀을 설치하는 경우에, 비트라인상(BIT0)와…(BIT7)와…(BIT56)와…(BIT63)와을 통한 신호가 각각 입력되는 센스앰프(S1)~(S7),…(S56)…(S63)에서는 FET쌍(Jφa)와 (Jφb)…(J7a)와 (J7b)…(J56a)와 (J56b)…(J63a)와 (J63b)의 드레인으로 연결하고, Y-어드레스 신호의 하위 3비트(Y2), (Y1), (Yφ)가 (Y2), (Y1), (Y0)부터,,의 값으로 각각 입력되는 8개씩의 NOR게이트(Nφ)…(N7)…(N56)…(N63)의 출력이 게이트로 입력되는 8개씩의 FET쌍(Jφa)와 (Jφb)…(J7a)와 (J7b)…(J56a)와 (J56b)…(J63a)와 (J63b)의 소오스에서는 FET쌍(J64a)와 (J63b)…(J71a)와 (J71b)의 드레인으로 연결하고, Y-어드레스 신호의 상위 3비트(Y5), (Y4), (Y3)가 (Y5), (Y4), (Y3)부터,,의 값으로 각각 입력되는 NOR게이트(N64)…(N71)의 출력이 게이트로 인가되는 FET쌍(J63a)와 (J64b)…(J71a)와 (J71b)의 소오스에서는 센스앰프 출력라인과 연결하여 선택된 메모리 셀에 저장된 정보의 신호가 Y-어드레스 신호의 하위 3비트(Y2), (Y1), (Yφ) 및 상위 3비트(Y5), (Y4), (Y3)에 의해 선택되어 출력버퍼를 거쳐 출력되도록 구성함을 특징으로 하는 갈륨비소 S램의 비트라인 선택회로.When 64 x 64 memory cells are installed on the X and Y side, the bit line (BIT0) and … (BIT7) and … (BIT56) and … (BIT63) and Sense amplifiers S1 to S7 to which signals through the respective signals are input; (S56)... In S63, the FET pairs Jφa and (Jφb). J7a and J7b... J56a and J56b... Connect to the drains of (J63a) and (J63b), and the lower 3 bits (Y2), (Y1), and (Yφ) of the Y-address signal are from (Y2), (Y1), (Y0) , , 8 NOR gates Nφ each of which are input as a value of. (N7)... (N56)... 8 pairs of FETs Jφa and (Jφb) in which the output of (N63) is input to the gate. J7a and J7b... J56a and J56b... In the source of (J63a) and (J63b), the FET pair J64a and (J63b). Connect to the drains of (J71a) and (J71b), and the upper 3 bits (Y5), (Y4), and (Y3) of the Y-address signal are from (Y5), (Y4), (Y3) , , NOR gates (N64), each input as a value of. FET pairs J63a and J64b to which the output of N71 is applied to the gate. In the sources of (J71a) and (J71b), the information signal stored in the selected memory cell in connection with the sense amplifier output line is divided into the lower 3 bits (Y2), (Y1), (Yφ) and the upper 3 bits (Y-address signal). Y5), (Y4), (Y3) is a bit line selection circuit of gallium arsenide S-RAM, characterized in that configured to be output via the output buffer. 비트라인 쌍(BITφ)와…(BIT7)와…(BIT56)와…(BIT63)와을 통한 신호가 각각 드레인으로 입력되는 FET쌍 (J100a)와 (J100b)…(J107a)와 (J107b)…(J156a)와 (J156b)…(J163a)와 (J163b)의 게이트에는 Y-어드레스 신호의 하위 3비트(Y2), (Y1), (Y0)가 (Y2), (Y1), (Y0)부터,,의 값으로 입력되는 NOR게이트(N100)~(N107)…(N156)…(N163)의 출력연결하고, 8개씩의 FET쌍(J100a)와 (J100b)…(J107a)와 (J107b)…(J156a)와 (J156b)…(J163a)와 (J163b)의 소오스가 입력단과 연결된 센스앰프 (S100)…(S107)의 출력단에서는 FET쌍(J164a)와 (J164b)…(J171a)와 (J171b)의 드레인과 연결하고, Y-어드레스 신호의 상위 3비트(Y5), (Y4), (Y3)가 (Y5), (Y4), (Y3)부터,,의 값으로 입력되는 NOR게이트(N164)~(N171)의 출력이 게이트로 인가되는 FET쌍 (J164a)와 (J164b)…(J171a)와 (J171b)의 소오스는 센스엠프 출력라인에 연결하여 선택된 메모리 셀에 저장된 정보의 신호가 출력버퍼를 통하여 출력되도록 구성함을 특징으로 하는 갈륨비소 S램의 비트라인 선택회로.Bit line pair (BITφ) and … (BIT7) and … (BIT56) and … (BIT63) and FET pairs J100a and J100b into which signals through the respective signals are input to the drains. J107a and J107b... J156a and J156b... In the gates of (J163a) and (J163b), the lower 3 bits (Y2), (Y1), and (Y0) of the Y-address signal are from (Y2), (Y1), (Y0). , , NOR gates (N100) to (N107) input as values of. (N156)... (N163) output connections and eight FET pairs J100a and J100b. J107a and J107b... J156a and J156b... A sense amplifier S100 connected to the input terminals of the sources J163a and J163b. At the output of S107, the FET pairs J164a and J164b are provided. Connect to the drains of (J171a) and (J171b), and the upper three bits (Y5), (Y4), and (Y3) of the Y-address signal are from (Y5), (Y4), (Y3) , , FET pairs J164a and J164b to which the outputs of the NOR gates N164 to N171, which are input as the values, are applied to the gate. And the source lines J171a and J171b are connected to the sense amplifier output line so that a signal of information stored in the selected memory cell is output through the output buffer. 상기 제1항 및 제2항에 있어서, 같은 입력을 받는 NOR게이트(N100)~(N163)는 하나만 사용하고 상기 NOR게이트(N100~N163)의 출력을 공통으로 이용하도록 한 갈륨비소 S램의 선택회로.The gallium arsenide S-RAM according to claim 1 or 2, wherein only one NOR gate N100 to N163 receiving the same input is used and the output of the NOR gates N100 to N163 are commonly used. Circuit. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019900016021A 1990-10-10 1990-10-10 BIT LINE CHOISE CIRCUIT OF GaAs SRAM KR930006632B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019900016021A KR930006632B1 (en) 1990-10-10 1990-10-10 BIT LINE CHOISE CIRCUIT OF GaAs SRAM

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019900016021A KR930006632B1 (en) 1990-10-10 1990-10-10 BIT LINE CHOISE CIRCUIT OF GaAs SRAM

Publications (2)

Publication Number Publication Date
KR920008762A true KR920008762A (en) 1992-05-28
KR930006632B1 KR930006632B1 (en) 1993-07-21

Family

ID=19304465

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019900016021A KR930006632B1 (en) 1990-10-10 1990-10-10 BIT LINE CHOISE CIRCUIT OF GaAs SRAM

Country Status (1)

Country Link
KR (1) KR930006632B1 (en)

Also Published As

Publication number Publication date
KR930006632B1 (en) 1993-07-21

Similar Documents

Publication Publication Date Title
KR930003153A (en) Semiconductor integrated circuit device
KR930008859A (en) DC-Current Data Output Buffer
KR940022561A (en) Output circuit of semiconductor memory
US4794276A (en) Latch circuit tolerant of undefined control signals
KR860002102A (en) Sample and Hold Circuit
KR920003311A (en) Memory device
KR890010922A (en) Semiconductor Integrated Circuits with DC Test
KR910006994A (en) Sense amplifier circuit
KR920008762A (en) Bit Line Selection Circuit of Gallium Arsenide S-RAM
KR870007511A (en) Data reading circuit
JPS63205890A (en) Semiconductor memory device
EP0379725A1 (en) Semiconductor device having output buffer circuit controlled by output control signal
KR940006073Y1 (en) Data reading circit
JP3574672B2 (en) Sense circuit
KR870004623A (en) Digital threshold detector
KR900002333A (en) Semiconductor integrated circuit
KR950033825A (en) Signal line switching circuit
KR930008084Y1 (en) Address transition detecting circuit
KR910012884A (en) Keypad switch input system
KR970076207A (en) Input stage circuit of Micro-Procesor
KR960025762A (en) Sensing Circuit of Flash Memory Cell
KR960015366A (en) Analog and digital port
JPS6041305A (en) Overload detecting circuit
KR970051112A (en) Sink RAM with Dual Output Ports
KR970055487A (en) Variable Slew Rate Control Logic Circuit

Legal Events

Date Code Title Description
A201 Request for examination
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20020628

Year of fee payment: 10

LAPS Lapse due to unpaid annual fee