JPS6041305A - Overload detecting circuit - Google Patents

Overload detecting circuit

Info

Publication number
JPS6041305A
JPS6041305A JP58149452A JP14945283A JPS6041305A JP S6041305 A JPS6041305 A JP S6041305A JP 58149452 A JP58149452 A JP 58149452A JP 14945283 A JP14945283 A JP 14945283A JP S6041305 A JPS6041305 A JP S6041305A
Authority
JP
Japan
Prior art keywords
signal
overload
level
load
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58149452A
Other languages
Japanese (ja)
Inventor
Nobumasa Misaki
信正 見崎
Takahito Kameoka
亀岡 孝仁
Yasuo Arai
康夫 新井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujikura Ltd
Oki Electric Industry Co Ltd
Original Assignee
Fujikura Ltd
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujikura Ltd, Oki Electric Industry Co Ltd filed Critical Fujikura Ltd
Priority to JP58149452A priority Critical patent/JPS6041305A/en
Publication of JPS6041305A publication Critical patent/JPS6041305A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To simplify the constitution of a circuit by detecting whether the input signal and the output signal of a driver circuit coincide with each other or not and outputting an overload signal on a basis of the detection result. CONSTITUTION:An input signal S1 is applied to an inverting amplifier (driver) 1 and an exclusive OR gate 5 of an overload detecting circuit 3. An output signal S2 amplified by the amplifier 1 is inverted by an inverter 4 and is applied to the other input of the gate 5. It is detected whether the input signal S1 and the output signal S2 coincide with each other or not by the detecting circuit 3; and if they do not coincide with each other, a load 2 is judged to be normal, and a load signal SE is not outputted. If they coincide with each other, the load signal SE is outputted; and thus, the constitution of the overload detecting circuit is simplfied.

Description

【発明の詳細な説明】 この発明は、ドライバ(増1陥器等)の負荷が過負荷状
態となった場合圧これン検出する過負荷検出回路に関す
る。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an overload detection circuit that detects pressure when the load of a driver (intensifier, etc.) becomes overloaded.

ドア イハり負荷が過負荷状態になると、通常ドライバ
が破損され、ざらにそりままにしておくと、火災等思わ
ぬ小数ンひき起こす。したがって、過負荷検出回路は種
々の装置において非常に重要である。ところで、従来の
過負荷検出回路はいずれも構成が複雑で、価格が高価と
なり、こりため、特に自動車等コストダウンが強く要求
される分野においては採用しにくいという問題があった
When the door is overloaded, the driver is usually damaged, and if left unattended, it can cause unexpected problems such as fire. Therefore, overload detection circuits are very important in various devices. By the way, all conventional overload detection circuits have complicated structures, are expensive, and are stiff, which makes them difficult to employ, especially in fields such as automobiles where cost reduction is strongly required.

そこでこの発明は構成が極めて簡嘔で、したがって安価
に製造することができる過負荷検出回路ビ提供するもの
士、ドライパリ入力信号と出力信号とが一致するか否か
乞検出し、この検出結果に基づいて過負荷信号?出力す
る回路からなるものである。
SUMMARY OF THE INVENTION Therefore, the present invention provides an overload detection circuit which has an extremely simple configuration and can be manufactured at low cost. Based on overload signal? It consists of an output circuit.

以−ド、図面乞参照しこの発明の実施例について説明す
る。第を図はこの発明crJ第tの実施例の構成ン示す
図であり、こり図において符号lは反転増幅器(ドライ
バ)、2はこの反転増幅器lによ。
Embodiments of the present invention will now be described with reference to the drawings. Figure 1 is a diagram showing the configuration of the tth embodiment of this invention. In the diagram, reference numeral 1 indicates an inverting amplifier (driver), and 2 indicates the inverting amplifier 1.

つて駆動される負荷、8はこの発明による過負荷検出回
路である。過負荷検出回路8は、その入力端が反転増幅
器1の出力端に接続されたインバータ4と、第1入力端
がインバータ4の出力端に、第λ入力端が反転増幅器1
0入力端に各々接続されたイクスクルーシブオアゲート
(以y、Hx、oRと略称する)5とから構成され、E
X 、OR5の出力端から過負荷信号5R(Hレベルの
信号ンが出力される。
The load 8 is an overload detection circuit according to the present invention. The overload detection circuit 8 has an inverter 4 whose input terminal is connected to the output terminal of the inverting amplifier 1, a first input terminal connected to the output terminal of the inverter 4, and a λ-th input terminal connected to the inverting amplifier 1.
It consists of exclusive OR gates (hereinafter abbreviated as y, Hx, and oR) 5 connected to the 0 input terminal, respectively, and
An overload signal 5R (H level signal) is output from the output terminal of X and OR5.

次に、上記回路の動作乞説明する。最初に、負荷2が正
常な場合について説明する。
Next, the operation of the above circuit will be explained. First, a case where load 2 is normal will be explained.

反転増幅器1り入力信号SIがLレベルの時は同増幅器
1の出力信号S2がHレベルとなり、負荷2が駆動され
、筐た、インバータ4の出力信号S、がLレベルとなる
。一方、信号S1がHレベルの時は、信号S2がLレベ
ルとなり、負荷2は駆動されず、また、信号S3がHレ
ベルとなる。
When the input signal SI to the inverting amplifier 1 is at L level, the output signal S2 of the amplifier 1 is at H level, the load 2 is driven, and the output signal S of the inverter 4 is at L level. On the other hand, when the signal S1 is at the H level, the signal S2 is at the L level, the load 2 is not driven, and the signal S3 is at the H level.

このように、負荷2が正常な場合は、ff1X・OR5
の第1.第2の入力端へ供給される信号が、入力信号S
、のレベルにかかわらず一致し、したがって、入力信号
S+カHレベル、Lレベルのいずれの場合もEX 、O
R5の出力信号がLレベルとなり、過負荷信号Sg<r
+レベル〕が出力されることはない。
In this way, if load 2 is normal, ff1X・OR5
No. 1. The signal supplied to the second input terminal is the input signal S
, and match regardless of the level of the input signal S+, therefore, EX , O
The output signal of R5 becomes L level, and the overload signal Sg<r
+level] is never output.

次に、負荷2が過負荷状態になると、入力信号S1がL
レベルの時信号S、がHレベルにならず、Lレベルにな
る。この結果、IIXx・OR5の第1入力端へHレベ
ルの信号、第コ入力端へLレベルの信号が供給され、E
X・OR5から過負荷信号(Hレベル)が出力される。
Next, when load 2 becomes overloaded, input signal S1 goes low.
When the signal S is at the high level, the signal S does not go to the high level but goes to the low level. As a result, an H level signal is supplied to the first input terminal of IIXx/OR5, an L level signal is supplied to the second input terminal, and E
An overload signal (H level) is output from XOR5.

を比較し、両者が一致しない場合(信号S、とS3とが
一致する場合)は負荷2が正常であるとみなして過負荷
信号8xを出力せず、両者が一致した場合(信号S1 
とS、とが一致しない場合)に過負荷信号8w乞出力す
る。
If they do not match (signals S and S3 match), it is assumed that load 2 is normal and the overload signal 8x is not output, and if they match (signal S1
and S do not match), an overload signal 8w is output.

第2図はこの発明の第2 QJ実施例(’J 傅5+2
1χ示す回路図であり、この回に示す回路が第1図に示
すもυと異なる点は、負荷2ン駆動する増幅器として非
反転増幅器7 (ドライバ)が用いられている点、およ
び、第1図のインバータ4の代わりにバッファアンプ8
が用いられている点である。この図に示す回路において
、負荷2が正常な場合は、入力信号S1がHレベル、L
レベルのいずれの場合においても、11.X、、OR5
の第1.第コ入力端の信号が一致し、したがってEX−
OR5の出力18号がLレベルとなり、過負荷信号Sw
(Hレベ/L/)が出力されることはない。三方、負荷
2が過負荷状態となった場合は、入力信号8mがHレベ
°ルI7)時、信号S2がHレベルとならず、Lレベル
になる。この結果、EX・OR5の第1入力端へLレベ
ルの信号、第コ入力端へHレベルの信号が供給され、E
X・OR5から過負荷信号5R(Hレベル)が出力され
る。
Figure 2 shows the second QJ embodiment ('J Fu5+2) of this invention.
The circuit shown in this section is different from the one shown in FIG. 1 in that a non-inverting amplifier 7 (driver) is used as the amplifier for driving the load 2, Buffer amplifier 8 instead of inverter 4 in the diagram
is used. In the circuit shown in this figure, when the load 2 is normal, the input signal S1 is at H level and L level.
In any case of level 11. X,,OR5
No. 1. The signals at the second input terminal match, so EX-
Output No. 18 of OR5 becomes L level, and overload signal Sw
(H level/L/) is never output. On the other hand, when the load 2 is in an overload state, when the input signal 8m is at the H level I7), the signal S2 does not go to the H level but goes to the L level. As a result, an L level signal is supplied to the first input terminal of EX/OR5, an H level signal is supplied to the second input terminal, and E
An overload signal 5R (H level) is output from the XOR5.

こりように、@、2図に示す回路においても、過負荷検
出回路8が信号S1 とS2との一致ケチェックする。
Similarly, in the circuit shown in Figure 2, the overload detection circuit 8 also checks whether the signals S1 and S2 match.

そして、この回路の場合は、両者が一致していない時に
過負荷信号SEA出力する。
In the case of this circuit, the overload signal SEA is output when the two do not match.

以上説明したように、こり発明によればドライバり人力
信号と出力信号とが一致するか否かを検出し、この検出
結果に基づいて過負荷信号ン出力するようにしたので、
溝数が極めて簡昨になり、したがって安価に製遺するこ
とができ、特に、自動電導コストダウンが要求される分
野vc用いて好適である。
As explained above, according to the present invention, it is detected whether or not the driver's manual input signal and the output signal match, and the overload signal is output based on this detection result.
The number of grooves is extremely small, and therefore it can be manufactured at low cost, and is particularly suitable for use in the field of VC where automatic conduction costs are required to be reduced.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図、第2図は各々この発明の第1.第2の実施例の
樺成訴す回路図である◇ l・・・・・・反転増幅器(ドライバ)、2・・・・・
・負荷、3・・・・・・過負荷検出回路、4・・・・・
・インバータ、5・・・°°・イクスクルーシプオアゲ
ート、7・・・・・・非反転増幅器(トライバ)、8・
・・・・バッファアンプ。 出願人 藤倉亀線株式会社 沖電気工業株式会社 〜1−じ
FIG. 1 and FIG. 2 respectively show the first part of this invention. This is a circuit diagram of the second embodiment ◇ l... Inverting amplifier (driver), 2...
・Load, 3... Overload detection circuit, 4...
・Inverter, 5...°°・Exclusive OR gate, 7...Non-inverting amplifier (triver), 8.
...Buffer amplifier. Applicant: Fujikura Kame Line Co., Ltd. Oki Electric Industry Co., Ltd. ~1-J

Claims (1)

【特許請求の範囲】[Claims] ドライバによって駆動される負荷が過AM状態となった
場合にこれを検出する過負荷検出回路において、呵記ド
ライバυ人力信号と、前記ドライバの出力信号とが一致
するか否か?検出し、この検出結果に基づいて過負荷信
号音出力する回路からなる過負荷検出回路。
In an overload detection circuit that detects when a load driven by a driver enters an excessive AM state, does the human power signal of the driver υ match the output signal of the driver? An overload detection circuit consisting of a circuit that detects an overload and outputs an overload signal sound based on the detection result.
JP58149452A 1983-08-16 1983-08-16 Overload detecting circuit Pending JPS6041305A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58149452A JPS6041305A (en) 1983-08-16 1983-08-16 Overload detecting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58149452A JPS6041305A (en) 1983-08-16 1983-08-16 Overload detecting circuit

Publications (1)

Publication Number Publication Date
JPS6041305A true JPS6041305A (en) 1985-03-05

Family

ID=15475426

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58149452A Pending JPS6041305A (en) 1983-08-16 1983-08-16 Overload detecting circuit

Country Status (1)

Country Link
JP (1) JPS6041305A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61211380A (en) * 1985-03-16 1986-09-19 Taniguchi Ink Seizo Kk Printing ink
JPS61211381A (en) * 1985-03-16 1986-09-19 Taniguchi Ink Seizo Kk Printing ink

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61211380A (en) * 1985-03-16 1986-09-19 Taniguchi Ink Seizo Kk Printing ink
JPS61211381A (en) * 1985-03-16 1986-09-19 Taniguchi Ink Seizo Kk Printing ink
JPH0149429B2 (en) * 1985-03-16 1989-10-24 Taniguchi Ink Mfg
JPH0149428B2 (en) * 1985-03-16 1989-10-24 Taniguchi Ink Mfg

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