KR920004993A - Computer system with bus arbitration logic - Google Patents
Computer system with bus arbitration logic Download PDFInfo
- Publication number
- KR920004993A KR920004993A KR1019900013261A KR900013261A KR920004993A KR 920004993 A KR920004993 A KR 920004993A KR 1019900013261 A KR1019900013261 A KR 1019900013261A KR 900013261 A KR900013261 A KR 900013261A KR 920004993 A KR920004993 A KR 920004993A
- Authority
- KR
- South Korea
- Prior art keywords
- bus
- computer system
- masters
- logic
- arbitration logic
- Prior art date
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Abstract
내용 없음No content
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.
제1도는 본 발명의 버스 중재로직의 개념을 나타내는 참고도.1 is a reference diagram showing the concept of bus arbitration logic of the present invention.
제2도는 제1도의 실시예도.2 is an embodiment of FIG.
Claims (2)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019900013261A KR920004993A (en) | 1990-08-28 | 1990-08-28 | Computer system with bus arbitration logic |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019900013261A KR920004993A (en) | 1990-08-28 | 1990-08-28 | Computer system with bus arbitration logic |
Publications (1)
Publication Number | Publication Date |
---|---|
KR920004993A true KR920004993A (en) | 1992-03-28 |
Family
ID=67542554
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019900013261A KR920004993A (en) | 1990-08-28 | 1990-08-28 | Computer system with bus arbitration logic |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR920004993A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100899951B1 (en) * | 2001-06-23 | 2009-05-28 | 프리스케일 세미컨덕터, 인크. | System and method for controlling bus arbitration during cache memory burst cycles |
-
1990
- 1990-08-28 KR KR1019900013261A patent/KR920004993A/en not_active Application Discontinuation
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100899951B1 (en) * | 2001-06-23 | 2009-05-28 | 프리스케일 세미컨덕터, 인크. | System and method for controlling bus arbitration during cache memory burst cycles |
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WITN | Withdrawal due to no request for examination |