KR920004993A - Computer system with bus arbitration logic - Google Patents

Computer system with bus arbitration logic Download PDF

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Publication number
KR920004993A
KR920004993A KR1019900013261A KR900013261A KR920004993A KR 920004993 A KR920004993 A KR 920004993A KR 1019900013261 A KR1019900013261 A KR 1019900013261A KR 900013261 A KR900013261 A KR 900013261A KR 920004993 A KR920004993 A KR 920004993A
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KR
South Korea
Prior art keywords
bus
computer system
masters
logic
arbitration logic
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Application number
KR1019900013261A
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Korean (ko)
Inventor
인희식
Original Assignee
한태희
주식회사 금성사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 한태희, 주식회사 금성사 filed Critical 한태희
Priority to KR1019900013261A priority Critical patent/KR920004993A/en
Publication of KR920004993A publication Critical patent/KR920004993A/en

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Abstract

내용 없음No content

Description

버스 중재 로직을 가진 컴퓨터 시스템Computer system with bus arbitration logic

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 본 발명의 버스 중재로직의 개념을 나타내는 참고도.1 is a reference diagram showing the concept of bus arbitration logic of the present invention.

제2도는 제1도의 실시예도.2 is an embodiment of FIG.

Claims (2)

중앙처리장치의 주변장치들 사이에서 하나의 공유버스와 함께 현재의 버스트랜잭션 제어기능의 다수버스마스터가 중개 수단으로 매개되는 컴퓨터 시스템에 있어서, 상기 중재수단은 복수의 버스마스터중 그 어느 하나가 우선 순위 마스터로 되고 이 우선순위 마스터외의 또 다른 마스터들은 상기 공유버스를 점령 사용하는 것이 대등하게 될 수 있는 버스중재로직(1)이 구비되어 있는 구성을 특징으로 하는 버스중재로직을 가진 컴퓨터 시스템.In a computer system in which a plurality of bus masters of the current bus transaction control function are mediated as intermediary means, with one shared bus among peripheral devices of the central processing unit, wherein the arbitration means is one of a plurality of bus masters. A computer system with a bus mediation logic, characterized in that it is provided with a bus mediation logic (1) that becomes a priority master and that other masters other than this priority master are comparable to occupying and using the shared bus. 제1항에 있어서, 상기 버스중재로직(1)은 마스터가 3개; 이들이 버스를 요구하는 상태를 BR0, BR1, BR2; 상태논리데이타치작업중인 신호 BUSY; 인터럽트 신호 INT라 가정할 때, 이는 로직식으로2. The bus arbitration logic (1) according to claim 1, further comprising three masters; The states in which they require buses include BR0, BR1, BR2; State logic data Working signal BUSY; Assuming the interrupt signal INT, this is logical 로 되고, 상기 식중는 각기In the above formula Each 로 이뤄짐을 특징으로 하는 버스중재로직을 가진 컴퓨터 시스템.A computer system with a bus mediation logic characterized by ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019900013261A 1990-08-28 1990-08-28 Computer system with bus arbitration logic KR920004993A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019900013261A KR920004993A (en) 1990-08-28 1990-08-28 Computer system with bus arbitration logic

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019900013261A KR920004993A (en) 1990-08-28 1990-08-28 Computer system with bus arbitration logic

Publications (1)

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KR920004993A true KR920004993A (en) 1992-03-28

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KR1019900013261A KR920004993A (en) 1990-08-28 1990-08-28 Computer system with bus arbitration logic

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100899951B1 (en) * 2001-06-23 2009-05-28 프리스케일 세미컨덕터, 인크. System and method for controlling bus arbitration during cache memory burst cycles

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100899951B1 (en) * 2001-06-23 2009-05-28 프리스케일 세미컨덕터, 인크. System and method for controlling bus arbitration during cache memory burst cycles

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