KR0152940B1 - High speed bus system by loading dispersion of bus - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus system of a digital system such as a microcontroller, and more particularly, to a high speed bus system by loading distribution of a bus that realizes high speed operation by loading distribution of a bus. As the loading is concentrated, parasitic resistance and capacitance are larger than other signal lines, resulting in signal delay, thereby limiting the operation speed of the entire system. However, in the present invention, the signal delay of the bus is distributed by distributing the bus loading. This saves time and can improve the overall operating speed of digital systems such as microcontrollers.

Description

High speed bus system by load distribution of bus

1 illustrates a conventional bus system.

2 is a diagram showing a high speed bus system by load distribution of the bus of the present invention.

3 is a detailed view of the FIG. 2 bus loading dispersion.

4 is a bus loading equivalent circuit diagram of FIGS. 1 and 2;

5 is a circuit diagram for measuring the signal delay time of FIGS.

FIG. 6 is a diagram illustrating signal delay time measurement results of FIGS. 1 and 2 according to FIG. 5. FIG.

* Explanation of symbols for main parts of the drawings

200: central processing unit 210: ROM

220: RAM 230: Peripheral device

240: bus loading dispersion unit 250: seabus

260: Fibus 241, 242: three-state inverter

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus system of a digital system such as a microcontroller, and more particularly to a high speed bus system by load distribution of a bus that realizes high speed operation by loading distribution of a bus.

In the conventional bus system, as shown in FIG. 1, the central processing unit 100 reads a command from the ROM 110 and decrypts it, and uses the RAM 120 as a data memory from the ROM 110. FIG. The data corresponding to the read command is read from the RAM 120 to operate the peripheral / input / output unit 130.

A series of operations of exchanging data between each block is always possible through the bus line 140.

Therefore, the signal delay time of the bus line 140 becomes one of important factors for determining the operating speed of the entire system.

However, in such a case, one bus line is used in common, and the loading is concentrated, so that parasitic resistance and capacitance are larger than other signal lines, resulting in signal delay, thereby lowering the operating speed of the entire system. There was a limiting problem.

Accordingly, the present invention aims at realizing a high speed operation by dispersing the load concentrated on the bus line in view of such a conventional problem, and the present invention having such an object will be described in detail.

2 is a diagram showing a high-speed bus system by the load distribution of the bus of the present invention. As shown therein, a CPU is connected between the central processing unit 200 and the ROM 210 and the RAM 220 to exchange data with each other. Bus loading disperser 240 for distributing the load of the seabus 250 by separating the switch 250 and the peripheral / input / output unit 230 from the seabus 250 and from the seabus 250. The separated peripheral / input / output unit 230 is connected to the bus-loading distributing unit 240 and configured as a picus 260 that exchanges data with each other.

On the other hand, as shown in FIG. 3, the bus-loading dispersing unit is transferred to the data bus line BUS_PO of the seabus line BUS_CO according to the input / output read / write signals I / O RD / WR. It consists of two tri-state inverters 241 and 242 that are different in direction from each other so that data of the bus line BUS_PO is transferred to the sea bus line BUS_CO. 242 may be expanded accordingly according to the number of bus lines.

The operation and effects of the present invention thus constructed will be described in detail.

Data is exchanged between the central processing unit 200, the ROM 210, and the RAM 220 through the Seabus 250, and the bus loading distribution unit 240 is connected to the Seabus 250 and the peripheral / input / output. By separating the unit 230, parasitic resistance and capacitance are dispersed.

In addition, the bus-loading disperser 240 and the peripheral device / I / O 230 is connected to the bus 260, the data exchange between each other, which ultimately data exchange between the sea bus 250 and the bus 260 The bus loading distribution unit 240 is made smoothly to reduce the delay time of the signal.

Meanwhile, the bus loading dispersion unit 240 will be described in more detail with reference to FIG. 3 as follows.

The tri-state inverters 241 and 242 can read data from the peripheral / input / output unit 230 connected to the Fig. 260 bus by the input / output read / write signal (I / O RD / WR). Or, it is operated to output the data from the sea bus 250 to the fibus 260, if the input / output read / write signal (I / O RD / WR) is a fixed position signal The three-state inverter 242 is enabled and operated so that data can be read from the 230 through the bus line BUS_PO.

On the other hand, when the input / output read / write signal I / O RD / WR is a low potential signal, the three-state inverter 241 operates to output data from the sea bus line BUS_CO to the bus line BUS_PO. As a result, the bus may be separated from the load.

The fourth turning parasitic of ssibeo switch as shown in shows an load equivalent circuit of the high-speed bus system according to the load distribution of the bus load equivalent circuit in the present invention the bus of a conventional bus system, conventionally, (a) the resistance (R _C ) And capacitance (C _C ) and parasitic resistance (R _P ) and capacitance (C _P ) of the fiber are not dispersed, (b) is the parasitic resistance (R _C ) and capacitance (C _C ) and A three-state inverter is added to distribute the parasitic resistance (R _P ) and capacitance (C _P ) of the bus.

5 is a circuit diagram for measuring a signal delay time of a high speed bus system using a bus loading equivalent circuit of a conventional bus system and a load distribution of a bus of the present invention, and FIG. 6 shows a result of measuring a signal delay time. As a result, as shown in the drawing, the delay time due to the load distribution of the bus is modeled as the worst case, and as a result, the output D _{OUT1 according} to the present invention has a conventional bus system with respect to the input D _in . The signal delay time was improved by 28% in the rising part and 32% in the falling part than the output (D _OUT2 ) of.

Thus, a circuit diagram for measuring a signal delay time of a high-speed bus system by a load equivalent circuit of a bus according to the present invention and a load distribution of the bus of the present invention, and FIG. 6 shows a result of measuring a signal delay time. As shown in the drawing, the delay time caused by the load distribution of the bus is modeled as the worst case, and compared with the conventional method, and the output D _{OUT1 according} to the present invention is the output of the conventional bus system (D _in ). D _OUT2 ) improved the signal delay time by 28% in the rising part and 32% in the falling part.

As a result, the signal delay time of the bus can be reduced by distributing the loading of the bus, that is, parasitic resistance and capacitance, thereby improving the overall operating speed of a digital system such as a microcontroller.

Claims (3)

Seabus connected to the central processing unit, ROM and RAM to exchange data with each other, a busloading disperser for distributing the loading of the seabus by separating peripherals / inputs and outputs from the seabus, and peripherals separated from the seabus A high-speed bus system by distributing loading of a bus, characterized in that the device / I / O unit is connected to a bus-loading distributing unit to form a bus that exchanges data with each other. 2. The bus load distributing unit of claim 1, wherein the bus-loading distributing unit is a two-state inverter having two directions different from each other in which the data of the seabus line is transferred to the busbus line or the data of the busbus line is transferred to the seabus line according to the input / output read / write signals. A high speed bus system by loading distribution of a bus, characterized in that the configuration. 3. The high-speed bus system according to claim 2, wherein the three-state inverter can be expanded accordingly according to the number of bus lines of sea buses and fibuses.