JPH0632218B2 - Semiconductor memory device - Google Patents

Description

The present invention relates to a semiconductor memory device.

[Conventional technology]

Conventionally, as a semiconductor memory device having a reset means for resetting a data bus line pair based on a change in an input address signal, a circuit configuration as shown in FIG. 4 has been known. It was as shown in FIG.

ABu ₀ , ABu ₁ ... ABu _{i in} FIGS. 4 and 5
Is one of the address buffers placed at the left end of the memory cell block on the LSI chip, A ₀ , A ₁ ... A _i are input address terminals input to the address buffers ABu ₀ , ABu _i ... ABu _i , ABu _{i + 1} , ABu _{i + 2} ... A
Bu _{i + j} is one of the other address buffers A _{i + 1} and A _{i + 2} placed at the right end of the memory cell block on the LSI chip.
... A _{i + j} are the address buffers ABu _{i + 1} and ABu, respectively.
_{i + 2} ... Input address terminal input to ABu _{i + j} , B ₀ ,
B ₁ ... B _i , B _{i + 1} , B _{i + 2} ... B _{i + j} are input on the input address terminals A ₀ , A _i ... A _i , A _{i + 1} , A _{i + 2} ... A _{i + j} A detection signal generated when the address changes, D is a delay circuit,
DB and DBB are data bus line pairs, T301 is a data bus line pair DB and DBB reset MOSFETs,
RE301 is a reset signal generation circuit that resets the data bus line pair DB and DBB, and φ301 is a reset signal. The address buffers ABu ₀ ... ABu _{i + j} buffer the input address signals and detect changes in the input address signals to generate detection signals B _{0 to} B _{i + j} .

The reset signal generation circuit RE301 uses all the detection signals B ₀ , B ₁ ... B _i , B _{i + 1} , B _{i + 2} ... B _{i + j} as input signals and, as shown in FIG. ABu
₀ ... ABu _i and ABu _{i + 1 to} ABu _{i + j} are placed at both ends of the memory cell group due to the block layout of the LSI chip.

Now, the input address signal terminals A ₀ , A ₁ ... A _i or
When at least one of the input address signals input to A _{i + 1} , A _{i + 2} ... A _{i + j} changes,
At least one detection signal among the input address transition detection signals B ₀ , B ₁ ... B _i , B _{i + 1} , B _{i + 2} ... B _{i + j} is generated corresponding to the changed input address signal, When the reset signal φ301 is not generated, the reset MOSFET T301 having the reset signal φ301 as a gate input is activated, and the data bus line pair DB and DBB are equalized in potential and reset. As a result, the operating speed of the sense amplifier for amplifying the read signal of the memory cell corresponding to the input address signal can be improved.

[Problems to be solved by the invention]

The above-described conventional configuration has one address buffer ABu.
_Since the distance between _{i + 1 to} ABu _{i + j} and the reset signal generation circuit RE301 increases, the detection signals B _{i + 1} , B _{i + 2} ... B
_Since the wiring capacity of _{i + j} becomes large, there is a drawback that it causes an access delay and an increase in operating current, and there is a problem that it cannot well cope with a high speed memory.

[Means for solving problems]

According to the present invention, in the semiconductor memory device having the reset means for resetting the data bus line pair based on the change of the input address signal, the first input address inputted from one end side of the data bus line pair. A first reset signal generating circuit that generates a first reset signal based on a change in the input address signal of the signal group; and a second input address signal group that is input from the other end side of the data bus line pair. A second reset signal generation circuit that generates a second reset signal based on a change in the input address signal is provided, and the data bus line pair is reset independently by the first reset signal and the second reset signal. A semiconductor memory device characterized by the above is obtained.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of the present invention, and FIG. 2 is a layout diagram of circuit blocks on an LSI of this embodiment.

1 and 2, A ₀ , A ₁ ... A _i are the first input address signal group, A _{i + 1} , A _{i + 2} ... A _{i + j} are the second input address signal group, and B ₀ , B ₁ ... B _i are first detection signal groups generated when the input address of the first input address signal group A ₀ , A ₁ , ... A ₁ changes, B _{i + 1} , B _{i + 2} . B _{i + j} is a second detection signal group generated when the input address of the second input address signal group A _{i + 1} , A _{i + 2} ... A _{i + j} changes,
RE101 is a first reset signal generation circuit which receives the first detection signal group B ₀ , B ₁ ... B _i , and RE 102 is a second reset signal generation circuit.
Detection signal group B _{i + 1} , B _{i + 2} ... B _{i + j} of the second reset signal generation circuit, φ 101 is a first reset signal generated from the first reset signal generation circuit RE 101,
φ102 is a second reset signal generated from the second reset signal generation circuit RE102, DR and DBB are data bus line pairs, and T101 is the first of the data bus line pairs DB and DBB whose gate inputs are the first reset signal. For resetting
OSFET and T102 are the second reset MOSFETs of the data bus line pair DB and DBB having the second reset signal as a gate input.

The reset signal generation circuit RE101 includes address buffers ABu _{0 to} AB arranged at the left end of the memory cell block.
and the detection signal B ₀ .about.B _i only inputs from u _i, the address buffer AB disposed at the right end of the memory cell blocks
u _i + 1 detection signal B _{i +} 1 ~B _i + _j from ~ABu _{i + j} is inputted to a reset signal generating circuit RE102.

Now, if at least one input address signal of the first input address signal group A ₀ , A ₁ ... A _i changes, then one of B ₀ , B ₁ ... B _i corresponding to the changed input address signal At least one of them is generated and the first reset signal φ101 is generated accordingly, and the reset MOSFET T101 whose gate input is the reset signal φ101 is activated to equalize and reset the data bus line pair DB, DBB.

Next, the second input address signal group A _{i + 1} , A _{i + 2} ... A _{i + j}
When at least one of the input address signals changes, the detection signal B corresponding to the changed input address signal
_At least one of _{i + 1} , B _{i + 2} ... B _{i + j} is generated, and accordingly, a second reset signal φ102 is generated, and a reset MO having the reset signal φ102 as a gate input is used.
SFETT102 is activated, and data bus line pair DB, D
BB is equipotentialized and reset.

FIG. 3 is a circuit diagram of the second embodiment of the present invention.

In this embodiment, the reset MOSFET T101 in the first embodiment is replaced with two reset MOSFETs.
201 and 202, and the reset MOSFET 102 are replaced with two reset MOSFETs 203 and 204, respectively, and the collectors of the pair of reset MOSFETs are connected to a predetermined potential.

As a result, in the present embodiment, the digit line pair DB, DBB
Is not limited to simply equipotentializing the data bus line pair DB,
Since DBB can be equalized to the above predetermined potential, it is convenient in terms of level matching with the next stage connected to the data bus line pair DB, DBB.

〔The invention's effect〕

As described above, the present invention divides a plurality of input address signals into two or more input address signal groups and generates the first reset signal based on the change of the input address signals of the first input address signal group. A first reset signal generating circuit for generating a second reset signal based on a change of the second input address signal, and a data bus line pair for connecting the first reset signal generating circuit to the first reset signal generating circuit. Since the first and second reset signals are reset independently, the first and second reset signal generating circuits can be arranged adjacent to the first and second address buffers, respectively. , And the parasitic capacitance of each of the first and second detection signals can be reduced, and the access speed can be increased and the current consumption can be reduced.

[Brief description of drawings]

FIG. 1 is a circuit diagram of the first embodiment of the present invention, and FIG.
2 is a circuit block diagram of an LSI chip according to the present invention, FIG. 2 is a second embodiment of the present invention, FIG. 4 is a circuit diagram of a conventional example, and FIG. 5 is a circuit on an LSI chip of the present conventional example. Each block diagram is shown. ABu ₀ , ABu ₁ ... ABu _i , ABu _{i + 1} , ABu _{i + 2}
… ABu _{i + j} … Address buffer, RE101, RE1
02, RE301 ... Reset signal generation circuit, T101,
T102, T201, T202, T203, T204,
T301 ... Reset MOSFET, DB, DBB ... Data bus line pair.

Claims (1)

[Claims] 1. A semiconductor memory device comprising a reset means for resetting a data bus line pair based on a change of an input address signal, wherein a first input is made from one end side of the data bus line pair.
A first reset signal generating circuit for generating a first reset signal based on a change in the input address signal of the input address signal group of, and a second reset signal input from the other end side of the data bus line pair.
A second reset signal generating circuit for generating a second reset signal based on a change in the input address signal of the input address signal group of the first reset signal and the second reset signal generating circuit. A semiconductor memory device characterized in that it is reset independently by a signal.