JP3123813B2 - Memory test circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus, and more particularly to a test circuit for a semiconductor memory device.

[0002]

2. Description of the Related Art Conventionally, as shown in FIG. 3, a test circuit of a semiconductor memory device has a plurality of data amplifiers 1 and output signals 603, 604, 605, and 606 are respectively applied to input terminals of an exclusive NOR circuit 7. Connected to the output terminal of the exclusive NOR circuit 7,
The determination signal 701 indicates a mismatch.

Next, the operation will be described. Data signal line pair 10
The data input to 1,102 to 401,402 are complementary signals to each other, and the data line selecting N-channel transistors 13,14,23,24,33,34,43,4
4 and becomes High by any one of the data signal selection signals 103 to 403, and is input to the data amplifier 1 via the true selection data signal line 501 and the false selection data signal line 502.

Each data amplifier outputs a plurality of read / write signal lines 601 to 606 as the data amplifier 1 amplifies the input data.

The exclusive NOR circuit 7 determines whether the read / write signal lines 603 to 606 match or not, and outputs a match signal 701 only when all the read / write signal lines 604 to 606 match.

[0006]

In this conventional match / mismatch determination circuit, the data signal line pair 101,
Since it is determined whether the signal lines selected from 102 to 401 and 402 are amplified by the data amplifier, the number of signal lines that can be determined is limited, and it is difficult to determine many signals simultaneously. there were.

In addition, in order to determine the coincidence or non-coincidence of many signals at the same time, the number of data amplifiers required is the same as the number of data to be determined, and the size of the determination circuit is increased.

SUMMARY OF THE INVENTION An object of the present invention is to provide a memory test circuit having a reduced circuit configuration and a high-speed memory circuit evaluation.

[0009]

To achieve the above object, a memory test circuit according to the present invention comprises a plurality of pairs of data lines, a plurality of pairs of P-channel transistors for judgment, and a plurality of N-channels for selecting data lines. A memory test circuit having a transistor pair, a precharge N-channel transistor, and a data amplifier , wherein the plurality of data line pairs include a true data line for inputting true value data, and an inverted value data. is intended to set the data line fake for inputting said plurality of judgment P-channel transistor pair,
Connected to the plurality of data line pairs and configured in a NAND structure
The data match / mismatch determination signal is
Is intended to force out from, the inverter comprises a plurality of de
When the data of the data line pair matches, the precharge level
Set one level of the selected data line pair to change
Is intended to clamp the value, the plurality of N-channel transistor pair data line selection is connected to the output side of the plurality of determination for the P-channel transistor pair, which selects the data line, said precharge N A channel transistor is connected to the input of the inverter which is the determination signal.
All SANYO precharging signal, the data amplifier
Receives the signal selected in the test mode as an input,
Match / mismatch depending on the judgment signal from the inverter
Ru Der outputs an output signal.

[0010] The memory test circuit according to the present invention comprises:
A plurality of data line pairs and a plurality of N-channel transistors for judgment
Star pairs and N-channel transistors for selecting multiple data lines
Data pair, a precharge P-channel transistor, and a
A memory test circuit having a data amplifier.
Multiple data line pairs provide true data input for true value data.
Data line and a fake data line for inputting inverted value data.
A plurality of N channel traffic for determination.
A transistor pair connected to the plurality of data line pairs;
It is configured in the ND structure, and it is used to determine whether data matches or not.
Signal from the inverter.
Data when multiple data line pairs match.
One of the selected data line pairs
It is intended to clamp the rectangular level of the set value, the double
N-channel transistor pairs for data line selection
Connected to the output side of the P-channel transistor pair
Select the data line,
P-channel transistor for the determination signal is
It precharges the input signal of the inverter,
The data amplifier selects the signal selected during the test mode.
Signal as input and the judgment signal from the inverter
And outputs an output signal of coincidence or non-coincidence.

[0011]

[0012]

As shown in FIG. 1 or FIG.
Channel (or N-channel) transistors 15, 16,
25, 26, 35, 36, 45, and 46, a true data signal line and false data signal lines 101, 102 to 40 are used.
By connecting each of the gates 1 and 402 to a gate to form a determination circuit having a NAND configuration, and inputting the determination result to the data amplifier 1 via the inverter 4, when all data on the data signal lines match, A match signal is output from the data amplifier 1. With such a configuration, it is possible to determine the coincidence and non-coincidence of a large number of data with a small circuit configuration.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

In FIG. 1, the memory test circuit according to the present embodiment has a plurality of data line pairs. Each data line pair is connected to a true data line 10 for inputting true value data precharged to a predetermined potential.
1,201,301,401, and a fake data line 1 for inputting data of a true value and an inverted value input on a true data line
02, 202, 302, and 402 as one set.

Each data line pair 101, 102-4
01 and 402 are connected to the sources of N-channel transistors 13, 14, 23, 24, 33, 34, 43 and 44 for data selection, and P-channel transistors 15, 16, 25, 26, 35 and 36, respectively. 45 and 46 are connected to the gates.

True data lines 101, 201, 301, 4
01 respectively connected to P-channel transistors 1
5, 25, 35, and 45 have a NAND structure in which the source and drain are connected in series, one end of which is connected to the power supply, and the other end of which is connected to the input end of the inverter 4.

Similarly, the false data lines 102, 20
Sources and drains of P-channel transistors 16, 26, 36, and 46 connected to 2, 302, 402 are connected in series, one end of which is connected to a power supply, and the other end is connected to an input terminal of an inverter 4. It has a structure.

Further, the N-channel transistor has a drain grounded to precharge the gate level of the inverter 4, a source connected to the input terminal of the inverter 4, and a gate connected to the precharge signal line 601.

True data lines 101, 201, 301, 4
01, N-channel transistors 13, 23,
33 and 43 are select data signal lines 501 whose drains are true.
And the false data lines 102, 202, 302, 4
02 connected to N-channel transistors 14, 24,
34 and 44 are select data signal lines 502 whose drains are false.
It is connected to the.

The N-channel transistors 13, 14,.
Gates of 23, 24, 33, 34, 43, 44 are connected to data signal selection signal lines 103, 203, 303, 4 respectively.
03 respectively.

On the other hand, the output terminal of the inverter 4 is connected to the source of the N-channel transistor 3 whose gate is connected to the mode selection signal line 602, and the drain of the N-channel transistor 3 is connected to the false selection data line 502. It is connected.

Further, the input terminal of the data amplifier 1 is connected to selected data signal lines 501 and 502, and the output terminal
The read / write data signal line 603 is connected.

Next, the operation will be described. Data signal line pair 10
1,102,201,202,301,302,40
1, 402 are precharged to the power supply (Vcc) in advance, and the input level of the inverter 4 is precharged to GND. When data is input to this data signal line pair, true data lines 101, 201, 301,
401 and fake data lines 102, 202, 302, 402
Either of these causes the potential to drop below Vcc.

This type of data line operates at V
data lines 101, 102, 201, 202, 301, 302, 4 which are clamped to cc and cause voltage changes.
01 and 402 also do not drop to GND, the data signal is received by the data amplifier 1 and the read / write signal line
A signal of cc or GND is output.

When all the data on the data signal line pair match, for example, when all the data are 0, the P-channel transistors 15, 25, 35, 45 of the true data lines 101, 201, 301, 401 Exceeds the threshold, the input level of the inverter 4 rises to Vcc, and in the test mode, the N-channel transistor 3 is turned on to lower the level of the false selected data line 502. In response to this signal, the data amplifier 1
Outputs "1" to indicate a match.

(Embodiment 2) FIG. 2 is a circuit diagram showing Embodiment 2 of the present invention.

In this embodiment, the data line pairs 101, 201,
This is the case where the precharge levels of 301 and 401 are precharged to GND, and the match / mismatch determination transistors are N-channel transistors 11, 12, and 2.
1, 2, 31, 32, 41, and 42, and the P-channel transistor 2 is used on the input side of the inverter 4. The operation is the same as that of the first embodiment, and the data amplifier 1 determines whether the data is matched or not. Output.

[0029]

As described above, according to the present invention, by connecting the gate of a transistor directly to a data signal line pair in a NAND structure and sending a coincidence signal to a data amplifier, a large number of data can be matched with a small circuit scale. This has the effect that the mismatch can be determined.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing a conventional example.

[Explanation of symbols]

Reference Signs List 1 data amplifier 2 P-channel transistor (for precharge) 3 N-channel transistor 4 inverter 5 N-channel transistor (for precharge) 7 exclusive NOR circuit 11, 12, 21, 22, 31, 32, 41, 42 N
Channel transistors 13, 14, 23, 24, 33, 34, 43, 44 N-channel transistors for data line selection 15, 16, 25, 26, 35, 36, 45, 46 P
Channel transistor

Claims (2)

(57) [Claims] 1. A memory test circuit having a plurality of data line pairs, a plurality of determination P-channel transistor pairs, a plurality of data line selection N-channel transistor pairs, a precharge N-channel transistor, and a data amplifier. a is, the plurality of data line pairs is for the set and the true data line for inputting data of a true value, and a data line of false inputs data inverted value, the plurality of determination P-channel transistor pair, the double use
Connected to a number of data line pairs and configured in a NAND structure.
The data match / mismatch judgment signal is sent from the inverter
It is intended to output force, the inverter, the data of a plurality of data line pairs match
Selected when the precharge level changes
Is to clamp one level of the data line pair to the set value.
There, a plurality of N-channel transistor pair data line selection is connected to the output side of the plurality of determination for the P-channel transistor pair, which selects the data line, the N-channel transistor for precharging, the-size
The input signal of the inverter is a constant signal all SANYO precharging, the data amplifier signal is selected during the test mode
Signal as input and the judgment signal from the inverter
Te, match, memory test circuit, characterized in der Rukoto outputs a mismatch of the output signal. 2. A plurality of data line pairs and a plurality of judgment N channels.
Channel transistor pair and N-channels for selecting a plurality of data lines
And a P-channel transistor for precharging.
Memory test circuit having transistor and data amplifier
A is, the plurality of data line pairs, true for inputting data of a true value
Data line and fake data line to input inverted value data
And the plurality of N-channel transistor pairs for determination are
Connected to a number of data line pairs and configured in a NAND structure.
The data match / mismatch judgment signal is sent from the inverter
The inverter outputs the data of a plurality of data line pairs that match.
Selected when the precharge level changes
A clamp to shall one level of the over line pair to the set value
The plurality of data line selecting N-channel transistor pairs
Is connected to the output side of a plurality of pairs of P-channel transistors for judgment.
The precharge P-channel transistor is connected to select a data line.
Precharge the inverter input signal, which is a constant signal
In this case, the data amplifier selects the signal selected in the test mode.
Signal as input and the judgment signal from the inverter
Output match / mismatch output signals
A memory test circuit.