JPS5823675B2 - semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor memory device with a large storage capacity and a fast read operation speed.

Semiconductor memory devices are becoming increasingly larger in capacity and are required to be faster.

Semiconductor storage devices connect memory units arranged in an IJ box shape to data lines, and form a current path between a specific data line and an input/output common line using a decoder signal, thereby controlling a specific memory unit. Access (read/write)
It is carried out.

During reading, by forming this current path, the parasitic capacitance of the data line and the input/output common line is charged and discharged by the transistor (for example, MOSFET) of the storage unit according to the state of the storage unit, and the input/output common line is Change the potential.

For this reason, as the capacitance increases, the parasitic capacitance of the input/output common line increases, and the change in potential of the input/output common line slows down, which is a cause of hindering speed-up.

FIG. 1 shows this type of conventional semiconductor memory device.

Here, 1 is a memory array consisting of mXn memory units 1', 2' is a data line to which m memory units 11 are connected, and 31 is a word line to which n memory units 1' are connected. , 2 and 3 are decoder circuits; γ is a MOSFET for selectively connecting the data line 2' and the input/output common line 5 by a decode signal Ai given from the decoder circuit 2;
4 is a write control circuit, 6 is an amplifier that magnifies the voltage change on the input/output common line 5, 7 is a buffer for giving an output signal to the output terminal 8, and 9 is a clock ψ for driving the amplifier 6.
This is a circuit that generates 1.

Further, FIG. 2 shows an example of the memory unit 1', in which 10 is a terminal connected to a power supply, and 11 to 15 are MOSFETs.

In this device, when retrieving information from a memory unit 1', first a specific word line 3' is driven by a decoder circuit 3, and a specific MO8FET γ is made conductive by a decode signal Ai given from a decoder circuit 2. condition.

state.

In this state, the potential of the input/output common line 5 changes depending on the state of the selected memory unit 1'.

This potential change occurs in the form of charging and discharging the parasitic capacitance of the input/output common line 5 by the MO8FET γ, 15, 13, or 11.

By the way, in conventional devices of this kind, as the capacity increases, the parasitic capacitance of the input/output common line 5 increases significantly, and this large parasitic capacitance is stored in a limited size within the storage unit in addition to the parasitic capacitance of the data line. The battery must be charged and discharged using the MOSFET.

That is, the potential of the input/output common line 5 during reading. The disadvantage is that the change is slow and the read operation cannot be performed quickly.

Alternatively, in view of this point, there is a drawback that an amplifier 6 and its driving clock generator 9 must be provided for amplifying the potential change of the input/output common line 5.

Furthermore, an amplifier 6 is provided. Even if the clock ψ
If an attempt is made to speed up the read operation by accelerating the timing of generation of 1, the potential change of the input/output common line 5 will not be large enough for the amplifier 6, resulting in a disadvantage that malfunctions are likely to occur.

The present invention has been made in order to solve the above-mentioned conventional drawbacks, and includes providing at least two read-only lines whose potentials are different from each other, and depending on the potential of a selected specific data line, between the read-only lines. In particular, by forming a current path to perform reading.

An object of the present invention is to provide a semiconductor memory device that can increase the speed of readout operations.

The present invention will be explained in detail below according to one embodiment.

FIG. 3 shows an embodiment of the invention.

In FIG. 3, 4' is a write control circuit, 5' is a common line for writing, 5'' is a write control line, 16 and 17 are read-only lines, and 20 is a decode signal A1 and data from the decoder circuit 2. Read-only lines 16 and 17 depending on the potential of line 21
conduction or non-conduction between two terminals connected to
The readout unit circuit which can be set to the state, 19 a terminal connected to a power supply, 18 a MOSFET for charging one of the read-only lines, and the rest are the same as those shown in FIG.

Further, FIGS. 4 and 5 show two configuration examples of the read unit circuit 20, and 21 to 24 are MOSFETs forming the read unit circuit 20.

In order to perform a read operation, first, the write control line 5'' is set to a low voltage to make the MO8FET 2' non-conductive, thereby disconnecting the write common line 5' and the data line 2'.

Next, M in the read unit circuit 20 is
OSFET 21 or 24 is brought into conduction.

As a result, a current path is formed or not formed between the read-only lines 16 and 17 depending on the potential state of the data line 2'.

In the configuration example shown in FIG. 4, this current path is 16-21-22-
17, and in the configuration example shown in FIG. 5, it is 16-23-17.

Since the dedicated line 17 is grounded, if a current path is not formed between 16 and 17 in accordance with the above two states, the potential of the read only line 16 will maintain the high potential charged by the MOSFET 18, and the potential of the read only line 16 will remain at the high potential charged by the MOSFET 18, If a current path is formed between 17 and 17, the potential of read-only line 16 will change to read unit circuit 2.
The level becomes as low as possible by the ratio of the size of MOSFET 0 and the size of MOSFET 18.

This potential change of the read-only line 16 is taken out to the output terminal 8 via the buffer 7.

In this embodiment, data lines 2',
The structure is such that no path other than the power supply line is formed between the write common line 5' and the read-only lines 16 and 17.

Therefore, the only object that must be charged and discharged when the memory unit 1' is read is the data line 21, and as a result, the potential of the data line 2' can be quickly determined by the memory unit 1'. .

Furthermore, when a current path is formed between 1617 by the read unit circuit 20, the discharge target is only the read-only line 16, so the parasitic capacitance is reduced and the read-only line 16
The potential of is quickly determined.

That is, it is possible to speed up the read operation, and since the potential change of the read-only line 16 is large, the output buffer 7
There is no need to install an amplifier in front of the

In the embodiment shown in FIG. 3, the MOSFET 18 is always in a conductive state and the read-only line 17 is grounded.
A method of controlling the gate by T18 with a clock to completely reduce the low level of line 16 to zero and reducing power consumption.By grounding read-only line 17 through a MOSFET only when necessary, it is possible to It is easy to think of modifications such as relaxing the restriction that the outside of the board is at a low level.

Next, another embodiment of the present invention is shown in FIG.

In this case, divide the data line into two, and install two lines for each group.
Total of 4 read-only lines 16', 16", 17', 17
“is placed.

Reference numeral 25 denotes an integration circuit for combining the divided and extracted signals, which can be composed of, for example, an AND circuit 25' and a NOT circuit 25''.

26 is a circuit that generates the control signal B for the integrated circuit 25, and the other parts are the same as those in FIGS. 1 and 3.

In addition, in this embodiment, 4', 5', 2'', γl,
The writing system circuit corresponding to 5" is omitted.

In this embodiment, the upper half is a read-only line 16'.

17' to perform the same operation as described in the embodiment of FIG. 3, and the lower half also uses 1C517''.

Moreover, if we look at a certain read-only line, for example 16',
Since the number of data lines from which data must be read is halved by the division, the number of read unit circuits 20 is reduced, and the parasitic capacitance of the read-only line 16' is therefore reduced.

That is, a faster read operation is possible compared to the embodiment shown in FIG.

Alternatively, if the read operation is the same, the number of data lines can be doubled, and the total number of storage units can be increased to increase the capacity.

In the example of FIG. 6, the read-only lines 17' and 17
It is also possible to use a configuration in which three read-only lines are used as a whole, with the line " being common.

Furthermore, as a modification of the embodiment shown in FIG. 6, it is possible to arrange the data lines belonging to each group alternately so that there is no difference in read speed between the groups, or to make the number of divisions three or more. It will be done.

As described above, according to the present invention, it is possible to reduce the parasitic capacitance of the portion to be charged and discharged in the storage unit or readout unit circuit, so that the readout speed can be increased.

Furthermore, a large capacity storage device can be realized.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a conventional semiconductor memory device, FIG. 2 is a diagram showing an example of a storage unit, FIG. 3 is a diagram showing an embodiment of the present invention, and FIGS. FIG. 6 is a diagram showing an example of a read unit circuit, respectively, and FIG. 6 is a diagram showing another embodiment of the present invention. 1...Memory array, 1'...Storage unit, 2 and 3...Decoder circuit, 21...
...Data line, 31...Word line, 41...
...Write control circuit, 5'...Write common line, 5"...Write control line, 7...Output buffer, 16.16' , 16", 17, 17' and 1
γ'...Read-only line, 20...Read unit circuit, 25...Integrated circuit, 26...
...Control signal generation circuit.

Claims (1)

[Scope of Claims] 1. In a semiconductor memory device in which a memory unit is connected to a data line and a specific data line is selected by a decode signal to access the memory unit, at least two read-only lines are provided and the memory units are connected to each other. A semiconductor memory device characterized in that readout is performed by making the potentials different and forming a current path between the read-only lines according to the potential of the selected specific data line. 2. Claims characterized in that the formation of the current path is performed by a read unit circuit provided between the read-only lines in correspondence with the data lines, depending on the potential of the decode signal and the data line. 2. The semiconductor memory device according to item 1. 3. The semiconductor memory device according to claim 1 or 2, wherein no current path other than a line passing through a power supply line is formed between the data line and the read-only line. . 4. The semiconductor memory device according to claim 1, 2, or 3, wherein the data line is divided into a plurality of groups, and each group is provided with at least two read-only lines. 5. The semiconductor memory device according to claim 4, wherein a part of the read-only lines provided for each of the groups is commonly connected. 6. The semiconductor memory device according to claim 1, 2, 3, 4, or 5, wherein a current path is formed between the data line and the data line during writing.