KR920004402B1 - 디지탈 데이타 프로세서용 버스 인터페이스 회로 - Google Patents

디지탈 데이타 프로세서용 버스 인터페이스 회로 Download PDF

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Publication number
KR920004402B1
KR920004402B1 KR1019870012091A KR870012091A KR920004402B1 KR 920004402 B1 KR920004402 B1 KR 920004402B1 KR 1019870012091 A KR1019870012091 A KR 1019870012091A KR 870012091 A KR870012091 A KR 870012091A KR 920004402 B1 KR920004402 B1 KR 920004402B1
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KR
South Korea
Prior art keywords
data
signal
processor
bus
information
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Expired
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KR1019870012091A
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English (en)
Korean (ko)
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KR880010365A (ko
Inventor
아이. 루빈펠드 폴
케이. 제인 애닐
Original Assignee
디지탈 이큅먼트 코포레이션
마리에타 엠. 에디에르
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Publication of KR880010365A publication Critical patent/KR880010365A/ko
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Publication of KR920004402B1 publication Critical patent/KR920004402B1/ko
Expired legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4208—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus
    • G06F13/4217—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus with synchronous protocol

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Communication Control (AREA)
  • Microcomputers (AREA)
  • Non-Insulated Conductors (AREA)
  • Communication Cables (AREA)
KR1019870012091A 1987-02-24 1987-10-30 디지탈 데이타 프로세서용 버스 인터페이스 회로 Expired KR920004402B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US17,647 1987-02-24
US017647 1987-02-24
US07/017,647 US4831520A (en) 1987-02-24 1987-02-24 Bus interface circuit for digital data processor

Publications (2)

Publication Number Publication Date
KR880010365A KR880010365A (ko) 1988-10-08
KR920004402B1 true KR920004402B1 (ko) 1992-06-04

Family

ID=21783770

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019870012091A Expired KR920004402B1 (ko) 1987-02-24 1987-10-30 디지탈 데이타 프로세서용 버스 인터페이스 회로

Country Status (12)

Country Link
US (1) US4831520A (enExample)
EP (1) EP0283628B1 (enExample)
JP (1) JP2547424B2 (enExample)
KR (1) KR920004402B1 (enExample)
CN (1) CN1011356B (enExample)
AT (1) ATE125629T1 (enExample)
AU (1) AU589815B2 (enExample)
BR (1) BR8800537A (enExample)
CA (1) CA1287924C (enExample)
DE (1) DE3751426T2 (enExample)
IN (1) IN171632B (enExample)
MX (1) MX162024A (enExample)

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US4965717A (en) * 1988-12-09 1990-10-23 Tandem Computers Incorporated Multiple processor system having shared memory with private-write capability
AU625293B2 (en) * 1988-12-09 1992-07-09 Tandem Computers Incorporated Synchronization of fault-tolerant computer system having multiple processors
JPH0687232B2 (ja) * 1988-12-19 1994-11-02 三菱電機株式会社 データ処理装置
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US5353429A (en) * 1991-03-18 1994-10-04 Apple Computer, Inc. Cache memory systems that accesses main memory without wait states during cache misses, using a state machine and address latch in the memory controller
US5291609A (en) * 1991-06-13 1994-03-01 Sony Electronics Inc. Computer interface circuit
US5265216A (en) * 1991-06-28 1993-11-23 Digital Equipment Corporation High performance asynchronous bus interface
US5471638A (en) * 1991-10-04 1995-11-28 Bull Hn Inforamtion Systems Inc. Bus interface state machines with independent access to memory, processor and registers for concurrent processing of different types of requests
US5414827A (en) * 1991-12-19 1995-05-09 Opti, Inc. Automatic cache flush
US5388237A (en) * 1991-12-30 1995-02-07 Sun Microsystems, Inc. Method of and apparatus for interleaving multiple-channel DMA operations
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WO1993018461A1 (en) * 1992-03-09 1993-09-16 Auspex Systems, Inc. High-performance non-volatile ram protected write cache accelerator system
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US5721882A (en) * 1994-08-05 1998-02-24 Intel Corporation Method and apparatus for interfacing memory devices operating at different speeds to a computer system bus
IES950209A2 (en) * 1995-03-24 1995-10-18 Lake Res Ltd Communication apparatus for communicating two microprocessors
US6260126B1 (en) 1998-06-05 2001-07-10 International Busines Machines Corporation Data storage subsystem having apparatus for enabling concurrent housekeeping processing while an input/output data transfer occurs
AU1458501A (en) * 1999-11-05 2001-06-06 Analog Devices, Inc. Generic serial port architecture and system
US6961796B2 (en) * 2001-07-26 2005-11-01 Hewlett-Packard Development Company, L.P. Extendable bus interface
US7133972B2 (en) * 2002-06-07 2006-11-07 Micron Technology, Inc. Memory hub with internal cache and/or memory access prediction
US7200024B2 (en) * 2002-08-02 2007-04-03 Micron Technology, Inc. System and method for optically interconnecting memory devices
US7117316B2 (en) * 2002-08-05 2006-10-03 Micron Technology, Inc. Memory hub and access method having internal row caching
US7149874B2 (en) * 2002-08-16 2006-12-12 Micron Technology, Inc. Memory hub bypass circuit and method
US7054971B2 (en) * 2002-08-29 2006-05-30 Seiko Epson Corporation Interface between a host and a slave device having a latency greater than the latency of the host
US7836252B2 (en) 2002-08-29 2010-11-16 Micron Technology, Inc. System and method for optimizing interconnections of memory devices in a multichip module
US7102907B2 (en) * 2002-09-09 2006-09-05 Micron Technology, Inc. Wavelength division multiplexed memory module, memory system and method
US7245145B2 (en) * 2003-06-11 2007-07-17 Micron Technology, Inc. Memory module and method having improved signal routing topology
US7120727B2 (en) * 2003-06-19 2006-10-10 Micron Technology, Inc. Reconfigurable memory module and method
US7260685B2 (en) * 2003-06-20 2007-08-21 Micron Technology, Inc. Memory hub and access method having internal prefetch buffers
US7107415B2 (en) * 2003-06-20 2006-09-12 Micron Technology, Inc. Posted write buffers and methods of posting write requests in memory modules
US7428644B2 (en) * 2003-06-20 2008-09-23 Micron Technology, Inc. System and method for selective memory module power management
US7133991B2 (en) * 2003-08-20 2006-11-07 Micron Technology, Inc. Method and system for capturing and bypassing memory transactions in a hub-based memory system
US7136958B2 (en) * 2003-08-28 2006-11-14 Micron Technology, Inc. Multiple processor system and method including multiple memory hub modules
US20050050237A1 (en) * 2003-08-28 2005-03-03 Jeddeloh Joseph M. Memory module and method having on-board data search capabilities and processor-based system using such memory modules
US7120743B2 (en) * 2003-10-20 2006-10-10 Micron Technology, Inc. Arbitration system and method for memory responses in a hub-based memory system
US7234070B2 (en) 2003-10-27 2007-06-19 Micron Technology, Inc. System and method for using a learning sequence to establish communications on a high-speed nonsynchronous interface in the absence of clock forwarding
US7788451B2 (en) 2004-02-05 2010-08-31 Micron Technology, Inc. Apparatus and method for data bypass for a bi-directional data bus in a hub-based memory sub-system
US7412574B2 (en) * 2004-02-05 2008-08-12 Micron Technology, Inc. System and method for arbitration of memory responses in a hub-based memory system
US7257683B2 (en) * 2004-03-24 2007-08-14 Micron Technology, Inc. Memory arbitration system and method having an arbitration packet protocol
US7447240B2 (en) * 2004-03-29 2008-11-04 Micron Technology, Inc. Method and system for synchronizing communications links in a hub-based memory system
US7213082B2 (en) 2004-03-29 2007-05-01 Micron Technology, Inc. Memory hub and method for providing memory sequencing hints
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US7363419B2 (en) * 2004-05-28 2008-04-22 Micron Technology, Inc. Method and system for terminating write commands in a hub-based memory system
KR101160566B1 (ko) * 2004-11-25 2012-06-28 텔레콤 이탈리아 소시에떼 퍼 아찌오니 이동 통신장비용 결합 ｉｃ 카드 및 무선 트랜시버 모듈
CN100524267C (zh) * 2007-02-15 2009-08-05 威盛电子股份有限公司 数据处理系统及数据处理方法
US20080282072A1 (en) * 2007-05-08 2008-11-13 Leonard Todd E Executing Software Within Real-Time Hardware Constraints Using Functionally Programmable Branch Table
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CN107978292A (zh) * 2017-12-31 2018-05-01 河南思维轨道交通技术研究院有限公司 一种ttl液晶接口到lvds接口的转换电路和转换方法
CN111813726B (zh) * 2020-07-10 2023-03-07 中科芯集成电路有限公司 控制信号从高速总线向低速总线的转换方法

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US4503535A (en) * 1982-06-30 1985-03-05 Intel Corporation Apparatus for recovery from failures in a multiprocessing system

Also Published As

Publication number Publication date
CN87107293A (zh) 1988-09-07
US4831520A (en) 1989-05-16
AU589815B2 (en) 1989-10-19
KR880010365A (ko) 1988-10-08
DE3751426D1 (de) 1995-08-31
AU8003587A (en) 1988-08-25
CN1011356B (zh) 1991-01-23
JPS63208963A (ja) 1988-08-30
BR8800537A (pt) 1988-09-27
CA1287924C (en) 1991-08-20
ATE125629T1 (de) 1995-08-15
EP0283628A2 (en) 1988-09-28
IN171632B (enExample) 1992-11-28
EP0283628B1 (en) 1995-07-26
DE3751426T2 (de) 1996-03-14
JP2547424B2 (ja) 1996-10-23
MX162024A (es) 1991-03-22
EP0283628A3 (en) 1990-05-16

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