KR920003675A - Base decision circuit of Viterbi error correction device - Google Patents

Base decision circuit of Viterbi error correction device Download PDF

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Publication number
KR920003675A
KR920003675A KR1019900011556A KR900011556A KR920003675A KR 920003675 A KR920003675 A KR 920003675A KR 1019900011556 A KR1019900011556 A KR 1019900011556A KR 900011556 A KR900011556 A KR 900011556A KR 920003675 A KR920003675 A KR 920003675A
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South Korea
Prior art keywords
coefficient
unit
base value
viterbi
signal
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KR1019900011556A
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Korean (ko)
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KR940008743B1 (en
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박일근
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정용문
삼성전자 주식회사
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Publication of KR920003675A publication Critical patent/KR920003675A/en
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Publication of KR940008743B1 publication Critical patent/KR940008743B1/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes

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  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Error Detection And Correction (AREA)

Abstract

내용 없음.No content.

Description

비터비 오류정정장치의 기저값 결정회로Base decision circuit of Viterbi error correction device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도의 a)는 종래기술에 의한 기저값 결정회로의 구성도, b)는 제1도의 a)에 따른 기저값 결정회로의 동작파형도.A) is a block diagram of a base value determination circuit according to the prior art, and b) is an operating waveform diagram of a base value determination circuit according to a) in FIG.

제2도는 본 발명에 의한 기저값 결정회로의 구성도.2 is a block diagram of a base value determination circuit according to the present invention.

제3도는 제2도에 따른 기저값 결정회로의 일실시예시도.3 illustrates one embodiment of a base value determination circuit according to FIG.

제4도는 제2도에 따른 기저값 결정회로의 동작파형도.4 is an operating waveform diagram of a base value determining circuit according to FIG.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

10 : 비터비복호부 20 : 동기오류검출부10: Viterbi decoder 20: Synchronous error detector

30, 50 : 제1 및 제2계수부 40, 60 : 제1 및 제2기저값 결정부30, 50: first and second coefficient unit 40, 60: first and second base value determiner

70 : 제3계수부 80 : 제3기저값 결정부70: third coefficient unit 80: third base value determination unit

90 : 쌍극철체부 100 : 클럭동기부90: dipole iron body 100: clock synchronization unit

Claims (3)

비터비 알고리즘을 이용한 비터비 오류정정장치에 있어서, 전송로를 통해서 입력되는 데이타신호를 복호화하여 정확한 정보신호를 출력하는 비터비복호부(10)와, 상기 비터비복호부(10)에서 출력되는 신호를 부호화하여 오류가 검출되는 빈도수를 검출하는 동기오류검출부(20)와, 상기 비터비복호부(10)에서 전송되는 단위평가시간신호에 따라서 동기오류검출부(20)에서 출력되는 펄스신호를 각각 카운팅하여 설정된 기저값을 초과할때 인식신호를 출력하는 제1, 및 제2계수부(30, 50)와, 오류검출 기저값을 각기 다르게 설정하여 상기 제1, 및 제2계수부(30, 50)에 전송하는 제1 및 제2기저값 결정부(40, 60)와, 상기 제1, 및 제2계수부(30, 50)에서 출력되는 인식신호들을 카운팅하여 설정된 기저값에 따른 또다른 인식신호를 출력하는 제3계수부(70)와, 상기 제3계수부(70)에 전송되는 오류검출 기저값을 설정하는 제3기저값 결정부(80)와, 상기 제3계수부(70)에서 출력되는 인식신호에 따라 제1, 및 제2계수부(30, 50)에서 각기 출력되는 인식신호들을 선택하여 출력하는 쌍극절체부(90)와, 상기 쌍극절체부(90)에서 선택된 인식신호에 따라 입력되는 클럭신호를 소정비트 이동시켜 비터비복호부(10)로 전송하는 클럭동기부(100)를 포함함을 특징으로 하는 비터비 오류정정장치의 기저값 결정회로.In the Viterbi error correction apparatus using the Viterbi algorithm, the Viterbi decoder 10 for decoding the data signal input through the transmission path and outputting the correct information signal, and the signal output from the Viterbi decoder 10 The synchronous error detection unit 20 which encodes the frequency detected by the error detection and the pulse signal output from the synchronous error detection unit 20 according to the unit evaluation time signal transmitted from the Viterbi decoder 10 are set. The first and second coefficient units 30 and 50 outputting the recognition signal when the base value is exceeded, and the error detection base value are set differently to the first and second coefficient units 30 and 50. Counting the first and second base value determination unit (40, 60) and the recognition signals output from the first and second coefficient unit (30, 50) to transmit another recognition signal according to the set base value A third coefficient unit 70 for outputting the third coefficient A third base value determiner 80 for setting an error detection base value transmitted to 70; and first and second coefficient units 30, according to a recognition signal output from the third coefficient unit 70; The dipole switching unit 90 selects and outputs the recognition signals respectively output from the 50 and the clock signal input according to the recognition signal selected by the dipole switching unit 90 to the Viterbi decoder 10. A base value determination circuit of a Viterbi error correction device, characterized in that it comprises a clock synchronization unit 100 for transmitting. 제1항에 있어서, 제1기저값 결정부(40)는 상기 제1계수부(30)가 작은 계수값을 갖도록 기저값을 설정하고, 제2기저값 결정부(60)는 상기 제2계수부(50)가 큰 계수값을 갖도록 기저값을 설정하여 초기 동기시에는 제1계수부(30)를 이용하여 동기를 시도하여 소요되는 시간을 단축하고, 동기된 후 전송로의 신호대잡음비가 변해도 동기가 유지되도록 제2계수부(50)를 작동시키는 것을 특징으로 하는 비터비 오류정정장치의 기저값 결정회로.The method of claim 1, wherein the first base value determiner 40 sets the base value so that the first coefficient unit 30 has a small coefficient value, and the second base value determiner 60 sets the second coefficient. By setting the base value so that the unit 50 has a large coefficient value, the time required for synchronization is reduced by using the first coefficient unit 30 during initial synchronization, and even if the signal-to-noise ratio of the transmission path is changed after synchronization. A base value determination circuit of a Viterbi error correction device, characterized in that for operating the second coefficient unit (50) to maintain synchronization. 제1항에 있어서, 제3계수부(70)는 다상 이동변조 방법에 의해서 변조된 데이타신호가 비터비복호부(10)에 입력될때 이 비터비복호부(10)의 위상동기 변위는 위상수만큼 일어나므로 상기 제1, 및 제2계수부(30, 50)의 작동이 전환되는 시점을 결정하기 위하여 초기에 위상변위가 일어날 수 있는 위상수만큼 작은 계수값을 갖는 제1계수부(30)로 클럭동기를 변환한 후, 큰 계수값을 갖는 제2계수부(50)를 작동시키는 것을 특징으로 하는 비터비 오류정정장치의 기저값 결정회로.The phase synchronizing displacement of the Viterbi decoder 10 occurs by the number of phases when the data signal modulated by the polyphase motion modulation method is input to the Viterbi decoder 10. Therefore, in order to determine the timing at which the operation of the first and second coefficient units 30 and 50 are switched, the clock is first clocked to the first coefficient unit 30 having a coefficient value that is as small as the number of phases in which phase shift can occur. A base value determination circuit of a Viterbi error correcting device, characterized in that the second coefficient unit (50) having a large coefficient value is operated after the synchronization is converted. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019900011556A 1990-07-28 1990-07-28 Vitervi error correcting apparatus KR940008743B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019900011556A KR940008743B1 (en) 1990-07-28 1990-07-28 Vitervi error correcting apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019900011556A KR940008743B1 (en) 1990-07-28 1990-07-28 Vitervi error correcting apparatus

Publications (2)

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KR920003675A true KR920003675A (en) 1992-02-29
KR940008743B1 KR940008743B1 (en) 1994-09-26

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KR1019900011556A KR940008743B1 (en) 1990-07-28 1990-07-28 Vitervi error correcting apparatus

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KR940008743B1 (en) 1994-09-26

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