JPH10262223A - Data reproducing device for multiplexed tex video signal - Google Patents

Abstract

PROBLEM TO BE SOLVED: To stably reproduce character data by sampling level-shifted digital video signals based on clock signals. SOLUTION: A clock run-in(CRI) detection circuit 12a detects whether or not CRI signal components are included for more than a prescribed cycle number in digital video signals from an A/D conversion circuit 11, based on CRI cycle number detection signals from a CRI cycle number detection circuit 17, and outputs CRI signals. A slice level decision circuit 13 integrates the CRI signals and outputs slice level decision signals provided with a level corresponding to the average value. A DC level slice circuit 15 slices the center of the amplitude of the digital video signals VIDEOO time-adjusted in a delay circuit 14 based on the slice level decision signals. A data reproducing circuit 16 samples the level-shifted digital video signals based on the clock signals generated in a data reproducing clock generation circuit 20 and reproduces the character data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a character multiplexed video signal data reproducing apparatus for reproducing character data from a character multiplexed video signal demodulated from a received signal of a character multiplexed television broadcast, and more particularly to a character multiplexed video signal reproducing apparatus. The present invention relates to a device for generating a clock signal for reproducing character data from a synchronizing signal for character data identification added to a signal, and is used for, for example, a television receiver, a video tape reproducing device, and the like.

[0002]

2. Description of the Related Art A character multiplexed video signal contains character information in the form of character data or font data during a vertical scanning period of a video signal. CRI
A bit synchronization signal called a (clock run-in) signal and a byte synchronization signal called an FC (framing code) signal are sequentially added.

In the standard of the character multiplexed video signal, as shown in FIG. 7, a CRI signal is a pulse signal of 16 (8 cycles) having a pattern of "1010101010101010", and an FC signal is a pattern of "11100100". 8 pulse signals. The pulse period (frequency) of the CRI signal is determined according to the type of the standard.

Conventionally, a character multiplexed video signal data reproducing apparatus detects a CRI signal in a character multiplexed video signal, generates a clock signal for character data reproduction, and reproduces character data based on the clock signal. ing.

FIG. 6 shows a conventional data reproducing apparatus for a character multiplexed video signal. FIG. 7 is a timing waveform chart showing an operation example of the data reproducing apparatus of FIG. FIG.
, A video signal output from, for example, a video signal system of a television receiver is branched and input to the video signal input terminal 10. As the video signal input, a text multiplexed video signal is input when receiving a text multiplex television broadcast, but a normal video signal is input when receiving a normal television broadcast.

A / D (analog / digital) conversion circuit 1
Reference numeral 1 denotes an A / D converter for converting a video signal input from the video signal input terminal 10 into a digital video signal.

[0007] The CRI detection circuit 12 includes “10101010” in the digital video signal input from the A / D conversion circuit 11.
It detects whether or not an 8-cycle CRI signal having a pattern of “10101010” is included, and outputs a CRI signal if the CRI signal is included.

[0008] The slice level determination circuit 13 is provided with the CR
It is to integrate the CRI signal input from the I detection circuit 12 and output a slice level determination signal having a level corresponding to the average value.

The data reproduction clock generation circuit 20 detects a CRI signal input from the CRI detection circuit 12 and generates a clock signal for reproducing character data. The clock generation circuit 21 and the CRI level determination circuit 22
And a clock selection circuit 23.

The clock generation circuit 21
A two-phase clock signal having a frequency twice as high as that of the RI signal but asynchronous with the CRI signal (generally, a first clock signal CLK1 and a second clock signal CLK1, which are in opposite phases to each other)
2) is generated.

[0011] The CRI level determination circuit 22 is provided with the CRI
The level of the output signal of the RI detection circuit 12 is checked at the rising timing of each of the two-phase clock signals CLK1 and CLK2, and the magnitude relationship between the two series of check levels is determined, and the logic level differs according to the magnitude relationship. The determination signal CLKSEL is output.

The clock selection circuit 23 is provided with the CRI
The two-phase clock signal output CL of the clock generation circuit 21 according to the logic level of the judgment output of the level judgment circuit 22
It is composed of a combination of logic circuits such as AND gates and OR gates so that one of the K1 and CLK2 with the higher check level is selected and output as a data reproduction clock.

On the other hand, the delay circuit 14 delays the digital video signal input from the A / D conversion circuit 11 in accordance with the time required until the data reproduction clock generation circuit 20 generates a clock signal (time adjustment). Do).

The DC level slice circuit 15 receives the digital video signal whose time has been adjusted by the delay circuit 14, and determines the center of the amplitude of the digital video signal based on the slice level determination signal from the slice level determination circuit 13. It is to slice.

The data reproduction circuit 16 reproduces character data by sampling the digital video signal level-shifted by the DC level shift circuit 15 based on the clock signal generated by the data reproduction clock generation circuit 20. The data reproducing circuit 16
The subsequent circuit (not shown) performs necessary processing on the reproduced character data (reproduced data).

By the way, depending on the circumstances of the country or region where text multiplex television broadcasting is carried out (such as the standard achievement standards of broadcasting stations or the propagation conditions of broadcast radio waves), even when receiving text multiplex television broadcasting, video signals may not be transmitted. The video signal input to the input terminal 10 does not always include the CRI signal as specified. For example, the period of the CRI signal may be short or a part of the pulse of the CRI signal may be missing.

In this case, in the above-described conventional data reproducing apparatus, the CRI detecting circuit 12 determines whether or not the digital video signal contains a strictly eight-cycle CRI signal having a pattern of "1010101010101010". Is detected and the CRI signal is output when the CRI signal is included. Therefore, the CRI signal cannot be detected stably, and the clock signal for reproducing the character data cannot be generated stably. In some cases, data cannot be reproduced stably.

Therefore, for example, when manufacturing a device equipped with a data reproducing device for export-specification character multiplexed video signals, an 8-cycle CRI signal having a strictly "1010101010101010" pattern is included as described above. It is necessary to reconsider adopting the CRI detection circuit 23 for detecting whether or not there is an error.

[0019]

As described above, the conventional data reproducing apparatus for character multiplexed video signals can stably generate a clock signal for reproducing character data depending on the circumstances of the country or region where character multiplex television broadcasting is performed. There is a problem that character data cannot be stably reproduced due to the inability to generate the character data.

The present invention has been made in order to solve the above-mentioned problems, and it is possible to stably provide a clock signal for reproducing character data without being substantially affected by the circumstances of the country or region where text multiplex television broadcasting is performed. It is an object of the present invention to provide a character multiplexed video signal data reproducing apparatus that can generate and reproduce character data stably.

[0021]

According to a first aspect of the present invention, there is provided a data reproducing apparatus for a character multiplexed video signal, wherein the A / D conversion circuit converts the input of the character multiplexed video signal from analog to digital and outputs a digital video signal. A digital video signal is input, and it is detected whether or not a pulse signal having the same frequency as the CRI signal is included in the input signal. If the digital signal is included, a CRI cycle number detection signal indicating the cycle number of the pulse signal is detected. And a CRI input from the CRI cycle number detection circuit to determine whether or not the digital video signal input from the A / D conversion circuit contains a predetermined number of cycles or more of a CRI signal component.
Detected based on a cycle number detection signal.
A CRI detection circuit for outputting a signal, a slice level determination circuit for integrating a CRI signal input from the CRI detection circuit and outputting a slice level determination signal having a level corresponding to an average value thereof, and an input from the CRI detection circuit. A data reproduction clock generation circuit for detecting a CRI signal to generate a clock signal for reproducing character data;
A delay circuit that receives the digital video signal from the D conversion circuit and delays the digital video signal in accordance with a time required until a clock signal is generated by the data reproduction clock generation circuit; A digital video signal, a DC level slicing circuit for slicing the center of the amplitude of the digital video signal based on a slice level determining signal from the slice level determining circuit, and a digital level shifted by the DC level shifting circuit. A data reproduction circuit that reproduces character data by sampling a video signal based on a clock signal generated by the data reproduction clock generation circuit.

According to the character multiplexed video signal data reproducing apparatus of the second invention, an arithmetic processing circuit is further provided between the CRI cycle number detecting circuit and the CRI detecting circuit in the character multiplexed video signal data reproducing apparatus of the first invention. The arithmetic processing circuit is provided to capture each detection value data of the CRI cycle number detection circuit for a plurality of continuous scanning periods including a CRI signal, perform predetermined processing, and generate a predetermined CRI cycle number detection signal. The signal is output to a CRI detection circuit.

[0023]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 shows a data reproducing apparatus for a character multiplexed video signal according to a first embodiment of the present invention.

In FIG. 1, a video signal output from, for example, a video signal system of a television receiver is branched and input to a video signal input terminal 10. As the video signal input, a text multiplexed video signal is input when receiving a text multiplex television broadcast, but a normal video signal is input when receiving a normal television broadcast.

The A / D conversion circuit 11 A / D converts a video signal input from the video signal input terminal 10 and outputs a digital video signal. The CRI cycle number detection circuit 17 receives a digital video signal from the A / D conversion circuit 11, detects whether a pulse signal having the same frequency as the CRI signal is included in the input signal, and detects the signal. In this case, it is configured to output a CRI cycle number detection signal indicating the number of cycles of the pulse signal.

The CRI detection circuit 12a determines whether or not the digital video signal input from the A / D conversion circuit 11 includes a predetermined number of cycles or more of the CRI signal component. It is configured to detect based on the cycle number detection signal and to output a CRI signal when the CRI signal component is included.

The slice level determining circuit 13 is provided with the CR
It integrates the CRI signal input from the I detection circuit 12a and outputs a slice level determination signal having a level corresponding to the average value.

The data reproduction clock generation circuit 20 detects a CRI signal input from the CRI detection circuit 12a and generates a clock signal for reproducing character data. The clock generation circuit 21 and the CRI level determination circuit 22
And a clock selection circuit 23.

The clock generation circuit 21
A two-phase clock signal having a frequency twice as high as that of the RI signal but asynchronous with the CRI signal (generally, a first clock signal CLK1 and a second clock signal CLK1, which are in opposite phases to each other)
2) is generated.

The CRI level judging circuit 22 calculates the CRI
The level of the output signal of the RI detection circuit 12a is checked at the rising timing of each of the two-phase clock signals CLK1 and CLK2, and the magnitude relationship between the two series of check levels is determined, and the logic level differs according to the magnitude relationship. The determination signal CLKSEL is output.

The clock selection circuit 23 is provided with the CRI
The two-phase clock signal output CL of the clock generation circuit 21 according to the logic level of the judgment output of the level judgment circuit 22
It is composed of a combination of logic circuits such as AND gates and OR gates so that one of the K1 and CLK2 with the higher check level is selected and output as a data reproduction clock.

On the other hand, the delay circuit 14 delays the digital video signal input from the A / D conversion circuit 11 in accordance with the time required until the data reproduction clock generation circuit 20 generates a clock signal (time adjustment). Do).

The DC level slice circuit 15 is a digital video signal VIDE time-adjusted by the delay circuit 14.
O0 is input and the center of the amplitude of the digital video signal is sliced based on the slice level determination signal from the slice level determination circuit 13.

The data reproduction circuit 16 reproduces character data by sampling the digital video signal level-shifted by the DC level shift circuit 15 based on the clock signal generated by the data reproduction clock generation circuit 20.

A circuit (not shown) at the subsequent stage of the data reproducing circuit 16 performs necessary processing on reproduced character data (reproduced data). According to the data reproducing apparatus according to the first embodiment, character multiplex television broadcasting is performed depending on the circumstances of the country or region where the character multiplex television broadcasting is performed (such as the standard achievement standard of a broadcasting station or the propagation condition of broadcast radio waves). Even if the video signal input does not include the CRI signal as specified in the standard even when receiving the CRI signal, the CRI cycle is performed even if the pulse signal having the same frequency as the CRI signal is less than the number of cycles in the CRI signal standard in the video signal input. As long as the number of detected signals is equal to or greater than the number detected by the number detection circuit 17, the CRI signal can be stably detected, a clock signal for reproducing character data can be generated stably, and the character data can be reproduced stably.

Therefore, for example, when manufacturing a device equipped with a data multiplexing device for a text multiplexed video signal of export specifications, the data multiplexing device according to the first embodiment is employed to provide a character multiplexing television broadcast. Character data can be stably reproduced without being affected by the circumstances of the country or region where the character data is reproduced.

In the first embodiment, the CRI
The CRI cycle number detection signal output from the cycle number detection circuit 17 is used directly in the digital video signal.
It is detected whether the signal is included or not. However, each detection value data of the CRI cycle number detection circuit 17 for a plurality of continuous scanning periods including the CRI signal is taken into an arithmetic processing circuit, and a predetermined process is performed. May be output to the CRI detection circuit, an example of which will be described below.

FIG. 3 shows a character multiplexed video signal data reproducing apparatus according to a second embodiment of the present invention. The data reproducing apparatus shown in FIG. 3 is different from the data reproducing apparatus shown in FIG. 1 in that an arithmetic processing circuit 30 is provided between the CRI cycle number detecting circuit 17 and the CRI detecting circuit 12a. Are the same, and are denoted by the same reference numerals as in FIG.

The arithmetic processing circuit 30 includes a storage circuit (memory) 31 for storing each detection value data of the CRI cycle number detection circuit 17 for a plurality of continuous scanning periods including a CRI signal; A minimum value detection circuit 32 that outputs a CRI cycle number detection signal corresponding to the minimum value among the plurality of stored data to the CRI detection circuit 12a.

That is, according to the data reproducing apparatus of the second embodiment, the same effect as described above can be obtained by basically the same operation as that of the data reproducing apparatus of the first embodiment. can get. In addition, data can be reproduced by selecting a clock signal having a more appropriate phase.

FIG. 4 shows a character multiplexed video signal data reproducing apparatus according to a third embodiment of the present invention. The data reproducing device shown in FIG. 4 is different from the data reproducing device shown in FIG. 3 in that a microcomputer (microcomputer) 40 formed on the same semiconductor chip as the circuits is used as the arithmetic processing circuit 30. However, since the other components are the same, the same reference numerals as in FIG. 1 are used.

FIG. 5 is a flowchart showing an example of an algorithm for processing the CRI cycle number detection signal of the microcomputer 40 in FIG. That is, the algorithm shown in FIG. 5 first takes in each detection value data of the CRI cycle number detection circuit 17 for a plurality of continuous scanning periods including a CRI signal, and stores and stores the data in a RAM (random access memory). . Next, arithmetic processing for searching for the data having the highest frequency among the plurality of captured data is performed, and a CRI cycle number detection signal corresponding to the data having the highest frequency is output to the CRI detection circuit 12a.

With the data reproducing apparatus according to the third embodiment, basically the same operation as that of the data reproducing apparatus according to the first embodiment can provide the same effects as those described above.

[0044]

As described above, according to the present invention, a clock signal for reproducing character data can be generated stably without being substantially affected by the circumstances of the country or region where the text multiplex television broadcasting is performed. A character multiplexed video signal data reproducing apparatus capable of stably reproducing data can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a character multiplexed video signal data reproducing apparatus according to a first embodiment of the present invention.

FIG. 2 is a timing waveform chart showing an operation example of the data reproducing apparatus of FIG.

FIG. 3 is a block diagram showing a character multiplexed video signal data reproducing apparatus according to a second embodiment of the present invention.

FIG. 4 is a block diagram showing an apparatus for reproducing a character multiplexed video signal according to a third embodiment of the present invention.

FIG. 5 is an exemplary flowchart showing an example of an algorithm of processing by the microcomputer in FIG. 4;

FIG. 6 is a block diagram showing a conventional data reproducing apparatus for a character multiplexed video signal.

FIG. 7 is a timing waveform chart showing an operation example of the data reproducing apparatus of FIG. 6;

[Explanation of symbols]

 Reference Signs List 10: video signal input terminal, 11: A / D conversion circuit, 12a: CRI detection circuit, 13: slice level determination circuit, 14: delay circuit, 15: DC level slice circuit, 16: data reproduction circuit, 17: CRI cycle Number detection circuit, 20: data reproduction clock generation circuit, 21: clock generation circuit, 22: CRI level determination circuit, 23: clock selection circuit.

Claims (6)

[Claims] 1. An A / D conversion circuit for converting a character multiplexed video signal input into an analog / digital signal and outputting a digital video signal, wherein the digital video signal is input, and C is included in the input signal.
A CR for detecting whether or not a pulse signal having the same frequency as the RI signal is included, and outputting a CRI cycle number detection signal indicating the number of cycles of the pulse signal when included.
An I cycle number detection circuit; and a CR outputting from the CRI cycle number detection circuit whether or not the digital video signal input from the A / D conversion circuit contains a predetermined number of cycles or more of a CRI signal component.
It is detected based on the I cycle number detection signal.
A CRI detection circuit that outputs an I signal; a slice level determination circuit that integrates a CRI signal input from the CRI detection circuit and outputs a slice level determination signal having a level corresponding to an average value thereof; A data reproduction clock generation circuit for detecting an input CRI signal and generating a clock signal for reproducing character data; a digital video signal input from the A / D conversion circuit; and a clock signal generated by the data reproduction clock generation circuit. A delay circuit for delaying the digital video signal in accordance with a time required to generate the digital video signal, a digital video signal time-adjusted by the delay circuit is input, and the slice level determination circuit determines the center of the amplitude of the digital video signal. DC level slicing based on the slice level determination signal from A data reproduction circuit for reproducing character data by sampling a digital video signal level-shifted by the DC level shift circuit based on a clock signal generated by the data reproduction clock generation circuit. A data reproducing apparatus for character multiplexed video signals, characterized in that: 2. A data reproducing apparatus for a character multiplexed video signal according to claim 1, wherein said data reproducing apparatus is provided between said CRI cycle number detecting circuit and said CRI detecting circuit and is used for a plurality of consecutive scanning periods including a CRI signal. A character multiplexed video signal further comprising: an arithmetic processing circuit that captures each detection value data of the CRI cycle number detection circuit, performs predetermined processing, and outputs a predetermined CRI cycle number detection signal to the CRI detection circuit. Data playback device. 3. A data reproducing apparatus for a character multiplexed video signal according to claim 2, wherein said arithmetic processing circuit converts each detected value data of said CRI cycle number detecting circuit for a plurality of continuous scanning periods including a CRI signal. A storage circuit for storing; and a minimum value detection circuit for outputting to the CRI detection circuit a CRI cycle number detection signal corresponding to a minimum value among a plurality of data stored in the storage circuit. Data reproduction device for character multiplexed video signal. 4. A data reproducing apparatus for a character multiplexed video signal according to claim 2, wherein the arithmetic processing circuit uses a microcomputer formed on the same semiconductor chip as each of the circuits to continuously perform a scanning period including a CRI signal. Capturing the respective detection value data of the CRI cycle number detection circuit for a plurality of times, and outputting a CRI cycle number detection signal corresponding to the most frequent data among the plurality of captured data to the CRI detection circuit. Character multiplexed video signal data reproducing device. 5. A data reproducing apparatus for a character multiplexed video signal according to claim 1, wherein said data reproducing clock generating circuit has a frequency twice as high as a frequency of a CRI signal included in said digital video signal. A clock generation circuit for generating a first clock signal and a second clock signal having phases opposite to each other, and checking a level of an output signal of the CRI detection circuit at a rising timing of each of the two-phase clock signals. , To determine the magnitude relationship between the two series of check levels,
A CRI level determination circuit that outputs a determination signal; and one of the two-phase clock signal outputs of the clock generation circuit having a higher check level selected from the two-phase clock signal outputs according to the determination output of the CRI level determination circuit, thereby reproducing data. And a clock selection circuit for outputting the data as a clock for use. 6. The character multiplexed video signal data reproducing apparatus according to claim 1, wherein the character multiplexed video signal input is a video signal output from a video signal system in a television receiver. A data reproducing apparatus for a character multiplexed video signal, characterized in that it is a branched signal input.