JPH089190A - Synchronization discrimination circuit - Google Patents

Abstract

PURPOSE:To allow the circuit to follow quickly new synchronization even when a transmission station is switched by calculating the result of a synchronization condition based on the presence of a horizontal synchronizing signal and the result of discriminating the synchronization condition based on the presence of a frame synchronizing signal. CONSTITUTION:Since a synchronization discrimination device 121 discriminates the synchronization condition in terms of lines based on a characteristic of a waveform of a received horizontal synchronizing signal, the device 121 is susceptible to the effect of noise. A C/N detector 123 accumulates the noise applied to a prescribed part of a digital signal led from an A/D converter 102 and when much noise is in existence, a signal is fed to an interrupt switch 124 to interrupt an out of synchronism signal from the synchronization discrimination device 121. A synchronization discrimination device 121 discriminates the synchronization condition when an input frame synchronizing signal is in existence in a timing when an internal frame synchronizing signal generator 114 generates the synchronizing signal. As a narrow band BPR is employed, the circuit operation is stable, but an out-of-synchronism signal is not outputted till a phase error is generated continuously. An arithmetic unit 125 applies the out of synchronism signal to the synchronization timing generator 113 when at least of the synchronization discrimination devices outputs the out-of-synchronism signal to allow the generator 113 to make reset to lock a new synchronizing signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for determining a synchronization state in a television receiver, particularly in a MUSE type HDTV signal decoding apparatus.

[0002]

2. Description of the Related Art The MUSE system is known as one of the systems for band-compressing and transmitting wideband television signals. For this MUSE method, see Ninomiya "MUS
E-Hi-Vision transmission system "(The Institute of Electronics, Information and Communication Engineers). An MU that receives this MUSE television signal and restores the original broadband television signal
As a phase synchronization circuit for the SE decoder or the high-definition receiver, for example, there is a system described in Japanese Patent Laid-Open No. 61-234138. The operation of this phase locked loop will be described below.

FIG. 8 is a block diagram showing an example of a conventional phase locked loop circuit. The phase synchronization circuit is an analog MUS
E signal input terminal 101, analog / digital converter 102, frame sync signal detector 103, frame sync phase comparator 104, and frame sync determiner 105
, The horizontal sync phase comparator 106, and the loop filter 10
7, a digital / analog converter 108, a voltage controlled oscillator 109, an internal horizontal sync generator 111, an internal frame sync generator 112, and a sync timing generator 11.
3 and an internal control signal generator 114.

The analog MUSE signal input from the analog MUSE signal input terminal 101 is a voltage controlled oscillator 1
It is converted into a digital signal by the analog / digital converter 102 which operates by the resampling clock output from the signal 09, and is guided to the frame sync signal detector 103 and the horizontal sync phase comparator 106. Frame sync signal detector 10
3 detects a frame synchronization signal from the inputted digital signals and outputs a detected frame synchronization signal. On the other hand, the horizontal sync phase comparator 106 detects the phase difference between the horizontal sync signal of the input digital signal and the internal horizontal sync signal guided from the internal horizontal sync generator 111, and the loop filter 107 and the digital / analog converter 108. The phase control of the voltage controlled oscillator 109 is performed through. The resampling clock output from the voltage controlled oscillator 109 is
Horizontal sync generator 111, internal frame sync generator 112
The frequency is divided by to generate an internal horizontal synchronizing signal and an internal frame synchronizing signal. The internal control signal generator 114 generates an internal control signal based on the internal horizontal sync signal and the internal frame sync signal. Frame synchronization phase comparator 104
Is a frame synchronization signal detector 103 during a gate period having a predetermined range with reference to the internal frame synchronization signal.
The phase comparison is performed depending on whether or not there is a detected frame synchronization signal output by the. If the phase difference is outside the predetermined range,
That is, if there is no detected frame synchronization signal in the gate period, the frame synchronization phase comparator 104 outputs a phase error signal. Here, since the phase change of the detected frame synchronization signal is detected in clock units, even a phase shift of one clock can be regarded as a phase error. The frame synchronization determiner 105 outputs an out-of-synchronization signal when this phase error signal continues for a predetermined period. The synchronization timing generator 113 outputs a reset pulse at the timing at which the detected frame synchronization signal of the frame synchronization detector 103, which is first input after this out-of-synchronization signal, is input. By this reset pulse, the loop filter 107, the internal horizontal sync generator 111, the internal frame sync generator 112, and the frame sync determiner 105 are reset to a predetermined initial state, so that the frame sync timing of the received MUSE signal and the internal frame sync. Match the timing.

[0005]

In the above-mentioned conventional example, the frame synchronization determiner 105 outputs the out-of-synchronization signal when the phase error signal is continuously input a predetermined number of times in the unit of internal frame synchronization. There is. Therefore,
When the synchronization of the input signal becomes discontinuous due to the switching of the transmitting station such as satellite broadcasting, the out-of-synchronization signal judged by the discontinuity of the synchronization is output after a predetermined frame period from the time of switching the input signal. It Therefore, in the receiver,
This discontinuity in synchronization is determined, and the input signal after switching during the period until the new synchronization is pulled is decoded in the synchronization phase before switching. As a result, the synchronization signal, the video signal, and the control signals that are time-division-multiplexed in the MUSE signal cannot be processed at regular timings, and the influence thereof is noticeable as a strange video disturbance in the reproduced video after decoding. Appears. In particular, in the conventional configuration, a distorted image is displayed at a visually detectable level of several frame periods, which gives the viewer an unpleasant feeling of being very hard to see.

An object of the present invention is to switch a transmitting station as a means for reducing damage to a reproduced image due to a synchronization discontinuity in a device that receives a signal for switching a broadcast signal asynchronously like a high-definition broadcasting by satellite broadcasting. It is an object of the present invention to provide means for early detection of synchronization discontinuity and for detecting even when the reception C / N is deteriorated without malfunction.

[0007]

[Means for Solving the Problems]
First synchronization determination means for determining the synchronization state based on the presence / absence of a horizontal synchronization signal in the subsequent stage of the digital converter, and an analog MUS
Second synchronization determination means for detecting a frame synchronization signal from the E signal and determining the synchronization state based on the presence / absence thereof, a synchronization state determination result by the first synchronization determination means, and synchronization by the second synchronization determination means This is achieved by providing a calculation means for calculating the state determination result and guiding the calculation result of the calculation means as a synchronization loss signal to the synchronization timing generation means.

Further, the purpose is to provide a C / N detecting means for detecting the noise amount according to the received C / N, switch the arithmetic method in the arithmetic means according to the noise amount, and de-synchronize the arithmetic result. It is also achieved by introducing it as a signal to the synchronization timing generating means.

Furthermore, whether the purpose is an input signal,
Or VDP (Video Disc Player) or VTR
A control signal input terminal for inputting a discrimination signal capable of discriminating whether the signal is from a package medium such as a (video tape recorder) is provided, and the arithmetic means is operated according to the discrimination signal inputted from the control signal input terminal. It is also achieved by switching the calculation method of (1) and guiding the calculation result to the synchronization timing generating means as a synchronization loss signal.

[0010]

When the transmission station is switched, the frame synchronization phase and the horizontal synchronization phase of the received signal are discontinuous before and after the switching. In the first term means, the first synchronism determining means detects the phase discontinuity of the horizontal synchronism, judges the loss of synchronism earlier than the frame period, and outputs the synchronism error signal. Further, the second synchronization determination means detects a phase discontinuity of frame synchronization from the analog signal, determines out-of-synchronization by the frame cycle from this, and outputs a synchronization error signal. In the computing means, the out-of-sync signal output from the first synchronization determination means and the out-of-sync output from the second synchronization determination means are released according to the noise amount detected by the C / N detection means and the determination signal from the control signal input terminal. Based on the signal, the calculation result is output to the synchronization timing generating means as an out-of-synchronization signal. With the above operation, it is possible to early detect the loss of synchronization with respect to the synchronization discontinuity at the time of switching of the transmitting station, and perform the reset operation for pulling in a new synchronization signal after the switching.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of a sync decision circuit according to the present invention is shown in FIG. The synchronization determination circuit includes an analog MUSE signal input terminal 101 and an analog / digital converter 102.
A frame sync signal detector 103, a horizontal sync phase comparator 106, a loop filter 107, a digital
Analog converter 108, voltage controlled oscillator 109, internal horizontal sync generator 111, internal frame sync generator 1
12, a synchronization timing generator 113, and an internal control signal generator 114. The above is the same configuration as the conventional synchronization determination circuit.

In addition to the above configuration, the synchronization determination circuit according to the present invention has a first synchronization determination device 121, a second synchronization determination device 122, a C / N detector 123, and a cutoff switch 124.
And a calculator 125.

The operation of this embodiment will be described below. From the input terminal 101 of this embodiment, the internal signal generator 114 operates in the same manner as the conventional example. The analog MUSE signal input from the input terminal 101 is supplied to the analog / digital converter 1
02, and also to the second synchronization determiner 122. The analog MUSE signal input to the analog / digital converter 102 is converted into a digital signal and guided to the frame sync signal detector 103 and the horizontal sync phase comparator 106, and at the same time, the first sync decision unit 1
21 and the C / N detector 123. The first sync determiner 121 checks whether or not the horizontal sync signal of the digital signal is present at the timing of the internal horizontal sync signal output from the internal horizontal sync generator 111, and if it is determined that the horizontal sync signal is not detected, the sync is determined. The disconnection signal is supplied to the calculator 125 through the cutoff switch 124.

The horizontal sync signal is detected by the first sync determiner 121 by pattern matching the characteristics of the horizontal sync signal waveform shown in FIG. The feature of the first synchronization determiner 121 is that it is possible to determine out-of-synchronization on a line-by-line basis by using the horizontal synchronization signal, and the drawback is that the pattern matching method is used to detect the horizontal synchronization signal, so that it is affected by noise. That is, the horizontal sync signal cannot be detected when the reception C / N is deteriorated, and the probability of misjudgment as being out of sync increases. That is, as shown in FIG. 2, the pattern of the horizontal synchronizing signal is such that, at the time of start-up, a signal having an amplitude of ¼ until sample number 5 changes to ½ at sample number 6, and then at 3/4 at sample number 7.
Has reached an amplitude of 3/4. At the fall, sample number 5 has an amplitude of 3/4, sample number 6 has a half amplitude, and sample number 7 has a quarter amplitude.
Becomes the amplitude of. The pattern matching method is a method of detecting the pattern of the change in the amplitude to detect the rising or falling of the synchronizing signal. However, when the sample number 4 at the time of rising contains noise having an amplitude of 1/2,
The rising pattern cannot be detected because the rising pattern is determined to be different.

On the other hand, the second sync determiner 122 detects a frame sync signal from the analog MUSE signal guided from the input terminal 101 in an analog manner, and the detected frame sync signal is output from the internal control signal generator 114. If it does not exist at the timing of the line 1 line 2 signal, the synchronization is determined to be out of sync, and the out of synchronization signal is supplied to the arithmetic unit 125.

FIG. 3 shows an example of the configuration of the second synchronization judging device 122. The second synchronization determiner 122 has an input terminal 30.
1, an analog band pass filter (hereinafter referred to as an analog BPF) 302, a gate 303, a gate signal input terminal 304, a level detector 305, and an output terminal 306. The frame sync signal of the MUSE signal is arranged in the first line and the line 2 of the frame, and as shown in FIG.
The waveform in which the amplitude is inverted to 1 and 0 for every four Hz samples continues for 140 samples. That is 2.025M
It is a square wave of Hz. Therefore, analog BPF3
02: Analog MUS input from input terminal 301
The 2.025 MHz component of the frame synchronization signal is extracted from the E signal. The extracted signal is gated by the gate 303 from the gate signal input terminal 304, for example, by the gate signals for four lines including the line 1 and the line 2 where the frame synchronization signal exists, and the front and back thereof, and the level is detected. To the vessel 305. In the level detector 305, if the signals guided through the gates of only two lines, line 1 and line 2, have a predetermined level or higher, it is determined as a frame synchronization signal. If this condition is not satisfied, it is determined that the synchronization is lost and a synchronization error signal is output to the output terminal 3
It outputs to 06. With this configuration, a narrow band analog BPF
By using 302, the S / N can be improved and the frame synchronization signal can be detected even when the amount of noise is large. The features of the second synchronization determiner 122 are that determination is performed in frame units and stable out-of-synchronization determination is possible even when the reception C / N deteriorates due to noise.

Next, the arithmetic unit 125 is guided through the cutoff switch 124 to the first synchronization judgment unit 121.
When at least one of the out-of-synchronization signal from the second synchronization determination unit 122 and the out-of-synchronization signal from the second synchronization determiner 122 is input, an operation is performed to output the out-of-synchronization signal, and the out-of-synchronization signal of the operation result is output. Synchronous timing generator 1
Supply to 13. The C / N detector 123 detects the amount of noise corresponding to the received C / N by cumulatively adding noise added to a predetermined portion of the digital signal guided from the analog / digital converter 102. The noise amount and the received C / N have a relation that the noise amount is small when the received C / N is high and the noise amount is large when the received C / N is low. Therefore, if this noise amount is equal to or larger than a predetermined value, that is, if the received C / N is deteriorated, the C / N detector 123 cuts off the cutoff signal.
4 to the arithmetic unit 125 from the first synchronization decision unit 121.
Block the out-of-sync signal. This allows the receiving C
/ N Negative judgment when there is a lot of noise when deteriorated 1st
By using only the determination result of the second synchronization determiner 122, which is resistant to noise, without using the determination result of the synchronization determiner 121, the erroneous determination of loss of synchronization in the arithmetic unit 125 is prevented. on the other hand,
If this noise amount is less than or equal to a predetermined value, that is, the reception C
When / N is good, the cutoff switch 124 is in a state in which the first synchronization determination circuit 121 and the arithmetic unit 125 are connected, and the determination result of the first synchronization determination unit 121 is the arithmetic unit 125.
Be led to. In this case, the first synchronization determiner 121 and the second synchronization determiner 121
The result of the determination with the synchronization determination unit 122 in (1) is also used in the arithmetic unit 125 to determine the loss of synchronization. As a result, when the reception C / N is good as in normal reception, it is possible to determine whether the first synchronization determiner 121 is out of synchronization with the horizontal synchronization.
Out-of-sync can be determined early.

Next, the synchronization timing signal generator 11
When an out-of-synchronization signal, which is the calculation result of the arithmetic unit 125, is input, 3 enters a frame synchronization signal arrival waiting state,
When the detected frame sync signal is guided from the frame sync detector 103, a reset pulse is output in synchronization with this. With this reset pulse, the loop filter 1
07, the internal horizontal synchronization generator 111, and the internal frame synchronization generator 112 are reset to a predetermined initial state to synchronize the control signal internally generated with the frame synchronization timing of the received MUSE signal.

As described above, in the present embodiment, when the received C / N is good, it is possible to determine the out-of-synchronization on a line-by-line basis by the first synchronization determiner 121. Since the synchronization determiner 122 can determine stable out-of-sync on a frame-by-frame basis, a synchronization determination circuit that early detects synchronization discontinuity due to switching of the transmitting station and does not malfunction even when the reception C / N deteriorates. realizable.

Next, a second embodiment of the synchronization judgment circuit according to the present invention will be described with reference to FIG. The same numbers as those in the first embodiment shown in FIG. 1 have the same operations as described above. The difference between the synchronization determination circuit of this embodiment and the synchronization determination circuit of the first embodiment is that the arithmetic unit 125
In addition to that, the out-of-synchronization signal guided to the synchronization timing generator 113 is switched by the changeover switch 126 according to the amount of noise from the C / N detector 123. The changeover switch 126 is provided for the first synchronization determiner 1 if the noise amount detected by the C / N detector 123 is less than or equal to a predetermined value.
21 out of sync signal from sync timing generator 11
If the noise amount is equal to or larger than a predetermined value, the switching is performed so that the out-of-synchronization signal from the second synchronization determiner 122 is guided to the synchronization timing generator 113. With this configuration, when the reception C / N deteriorates, the first synchronization determiner 121 that may make an erroneous determination when there is a lot of noise.
By using only the determination result of the second synchronization determiner 122 that is resistant to noise without using the determination result of 1), there is a function of preventing an erroneous determination result from being introduced to the synchronization timing generator 113.

As described above, in the synchronization determination circuit of this embodiment, as in the synchronization determination circuit of the first embodiment, the reception C / N
Is good, it is possible to determine the loss of synchronization on a line-by-line basis using the first synchronization determiner 121, and to stabilize on a frame-by-frame basis using the second synchronization determiner 122 even when the reception C / N deteriorates. Since it is possible to judge out of synchronization,
It is possible to realize a synchronization determination circuit that can detect a synchronization discontinuity due to switching of transmitting stations at an early stage and that does not malfunction even when the reception C / N deteriorates.

Further, with the configuration of this embodiment, the arithmetic unit used in the synchronization determination circuit of the first embodiment is no longer necessary, which has the advantage of simplifying the circuit configuration.

Next, a third embodiment of the synchronization judgment circuit according to the present invention will be described with reference to FIG. The same number as that of the synchronization judgment circuit of the first embodiment shown in FIG. 1 has the same operation as described above. The synchronization determination circuit of this embodiment differs from the synchronization determination circuit of the first embodiment in that it comprises a frame synchronization phase comparator 104 and a frame synchronization determination device 105 used for synchronization determination in a conventional synchronization determination circuit. The synchronization determination means, the changeover switch 127, and the control signal input terminal 128 are added to the components, and the out-of-sync signal and the frame synchronization determination device obtained as a result of the operation by the operation unit 125 of the first embodiment of the present invention. The out-of-synchronization signal obtained at 105 is selected to generate the synchronization timing.

The operation of this embodiment will be described below. The first synchronization determiner 121, the second synchronization determiner 122, and the cutoff switch 124 operate in the same manner as in the first embodiment. Calculator 1
25 is synchronized when at least one of the out-of-sync signal from the first synchronization determiner 121 and the out-of-sync signal from the second synchronization determiner 122, which is guided through the cutoff switch 124, is input. The calculation is performed so as to output the out-of-sync signal, and the synchronous out-of-sync signal as the result of the operation is supplied to the changeover switch 127. Similarly to the conventional example, the frame synchronization determiner 105 supplies the out-of-synchronization signal to the changeover switch 127 when the frame synchronization phase comparator 104 continuously causes a phase error for a predetermined period. The changeover switch 127 is controlled by a determination signal input from the control input terminal 128. This discrimination signal is a signal that can discriminate whether the input signal is a broadcast signal or a signal from a package medium. Depending on the state of this discrimination signal, either the out-of-sync signal which is the calculation result in the arithmetic unit 125 or the out-of-sync signal from the frame synchronization determination unit 105 is selected, and the synchronization timing generator 1
An out-of-sync signal is supplied to 13. The reason for using the determination result of the frame synchronization determiner 105 is as follows. For example, at the time of inputting a signal from a package medium such as MUSE-LD (laser disk player in which a MUSE signal is recorded), the first synchronization determiner 121 and the second synchronization determiner 121 against the loss and the jitter of the frame synchronization signal due to the dropout. The determiner 122 cannot detect the synchronization signal and erroneously determines that the synchronization is lost. As a result, the synchronization is unnecessarily disturbed even though the synchronization is not actually lost. Therefore, at the time of inputting a signal such as MUSE-LD, the discrimination signal which can be discriminated as a signal from the package medium is given from the control signal input terminal 128,
The synchronization loss determination method is switched so that only the synchronization loss determination by the frame synchronization determiner 105 is used to keep the synchronization.

As described above, in the present embodiment, like the first embodiment, when the reception C / N is good, it is possible to determine the loss of synchronization on a line-by-line basis using the first synchronization determiner 121. The second synchronization determiner 1 even when the reception C / N deteriorates
Since it is possible to determine stable out-of-sync on a frame-by-frame basis using No. 22, a synchronization judgment circuit that early detects synchronization discontinuity due to switching of the transmitting station and does not malfunction even when the reception C / N deteriorates is realized. it can. Further, in the present embodiment, when a signal is input from the MUSE-LD or the like, by using only the determination result of the frame synchronization determiner 105 as in the conventional example, the synchronization is continuously maintained without the influence of the sync signal dropout or jitter. Therefore, malfunction can be prevented.

Next, a fourth embodiment of the synchronization judgment circuit according to the present invention will be described with reference to FIG. The same numbers as those in the third embodiment of FIG. 6 have the same operations as described above. This embodiment is different from the third embodiment in that the changeover switch 127 is eliminated, the second cutoff switch 129 and the second arithmetic unit 130 are newly added, and when the control signal is not input, the arithmetic unit 125 is added. The out-of-sync signal of the frame sync determiner 105 is used as the out-of-sync signal, and the out-of-sync signal of the frame sync determiner 105 is used as the out-of-sync signal when the control signal is input. It is about to be used as a signal.

The operation of the synchronization determination circuit of this embodiment will be described below. First synchronization determiner 121 and second synchronization determiner 1
22 and the cutoff switch 124 operate in the same manner as in the first embodiment. The calculator 125 is the first cutoff switch 1
An out-of-sync signal is output when at least one of the out-of-sync signal from the first sync determiner 121 and the out-of-sync signal from the second sync determiner 122, which is guided through 24, is input. To the second disconnection switch 129.
Through the second arithmetic unit 130. The second cutoff switch 129 is controlled by the determination signal input from the control input terminal 128. This discrimination signal is a signal that can discriminate whether the input signal is a broadcast signal or a signal from a package medium. Depending on the state of the discrimination signal, the out-of-synchronization signal which is the calculation result of the arithmetic unit 125 is cut off so as not to be guided to the second arithmetic unit 130. The frame synchronization determination unit 105 supplies the out-of-synchronization signal to the second arithmetic unit 130 when a phase error occurs continuously for a predetermined period in the frame synchronization phase comparator 104 as in the conventional example. The second computing unit 130 includes the second cutoff switch 1
The out-of-sync signal, which is the operation result of the arithmetic unit 125, which is guided through 29, and the out-of-sync signal from the frame synchronization determination unit 105 are operated, and the operation result is supplied to the synchronization timing generator 113 as the out-of-sync signal. As described above, unlike the third embodiment, the present embodiment is configured to always refer to the determination result of the frame synchronization determiner 105. The reason for this is as follows. In the third embodiment, when the received C / N deteriorates, the first synchronization determiner 121 is not used and only the second synchronization determiner 122 determines the loss of synchronization. However, the phase difference between the received signals before and after the switching is determined. If there are only a few samples, the second synchronization determiner 122 cannot determine the switching due to a problem in the determination performance. Therefore, in this embodiment, by using the frame synchronization determiner 105 that can determine the synchronization loss in clock units under the above conditions, the frame synchronization determiner 105 can always determine the synchronization loss in a predetermined period required for the determination. .

As described above, in this embodiment, as in the first embodiment, when the reception C / N is good, it is possible to determine the loss of synchronization on a line-by-line basis using the first synchronization determiner 121. The second synchronization determiner 1 even when the reception C / N deteriorates
Since it is possible to determine stable out-of-sync on a frame-by-frame basis using No. 22, synchronization discontinuity due to switching of the transmitting station can be detected early and synchronization that does not malfunction even when the reception C / N deteriorates. A decision circuit can be realized.

Further, in the present embodiment, as in the third embodiment, when the signal is input from the MUSE-LD or the like, only the judgment result of the frame sync judging unit 105 is used so that there is no influence of the sync signal dropout or jitter. Since the synchronization is maintained, malfunction can be prevented.

Further, in this embodiment, even when the received C / N is deteriorated and the phase difference between the received signals before and after the switching is only a few samples, the determination by the frame synchronization determiner 105 that can determine the loss of synchronization in clock units. By using the result, it is possible to realize a synchronization determination circuit that reliably determines out-of-synchronization in a predetermined period required for the determination by the frame synchronization determination unit 105.

[0031]

According to the present invention, the first sync determiner for determining the sync state based on the presence / absence of the horizontal sync signal, and the analog M
By using the synchronization state determination result with the second synchronization determiner that detects the frame synchronization signal from the USE signal and determines the synchronization state based on the presence or absence of the USE signal, the loss of synchronization due to sudden synchronization discontinuity of the input signal can be early and ensured. At the same time, the judgment method used for judging the synchronization state can be switched according to the received C / N and the input signal, so that the synchronization is not accidentally lost due to noise, etc. The synchronization processing can be followed.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a synchronization determination circuit according to a first embodiment of the present invention.

FIG. 2 is a waveform diagram of a horizontal sync signal of a MUSE signal.

FIG. 3 is a configuration diagram of a second synchronization determiner according to the present invention.

FIG. 4 is a configuration diagram of a frame synchronization signal of a MUSE signal.

FIG. 5 is a configuration diagram of a synchronization determination circuit according to a second embodiment of the present invention.

FIG. 6 is a configuration diagram of a synchronization determination circuit according to a third embodiment of the present invention.

FIG. 7 is a configuration diagram of a synchronization determination circuit according to a fourth embodiment of the present invention.

FIG. 8 is a configuration diagram of a conventional synchronization determination circuit.

[Explanation of symbols]

 101 analog MUSE signal input terminal 102 analog / digital converter 103 frame sync signal detector 104 frame sync phase comparator 105 frame sync determiner 106 horizontal sync phase comparator 107 loop filter 108 digital / analog converter 109 voltage controlled oscillator 111 Internal horizontal synchronization generator 112 Internal frame synchronization generator 113 Synchronization timing generator 114 Internal control signal generator 121 First synchronization determination device 122 Second synchronization determination device 123 C / N detector 124 Breaking switch 125 Computing device 126 Switching Switch 127 Second changeover switch 128 Control signal input terminal 129 Second cutoff switch 130 Second arithmetic unit 301 Input terminal 302 Analog band pass filter 303 Gate 304 Gate signal input terminal 305 level detector 306 output terminal

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Noboru Kojima, 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Inside Visual Media Research Center, Hitachi, Ltd. (72) Tatsuo Nagata 292 Yoshida-cho, Totsuka-ku, Yokohama, Kanagawa (72) Inventor, Kei Takashi Hasegawa, 216 Totsuka-cho, Totsuka-ku, Yokohama, Kanagawa Prefecture, Ltd. (72) In-house, Information and Video Media Division, Hitachi, Ltd. Toru Hasegawa, 2 Jinnan, Shibuya-ku, Tokyo 2-2-1 Japan Broadcasting Corporation Broadcast Center (72) Inventor Takashi Iwamoto Jinnan 2-2-1, Shibuya-ku Kyoto Kyoto Broadcasting Association Broadcast Center (72) Inventor Atsushi Yamakita 2 Jinnan, Shibuya-ku, Tokyo 2-1-1 Japan Broadcasting Corporation Broadcasting Center

Claims (4)

[Claims] 1. A synchronization determination circuit of a television receiver, wherein first synchronization determination means detects a horizontal synchronization signal from a received signal and determines a synchronization state based on the presence or absence thereof, and a frame synchronization signal from the received signal. Then, the determination result derived from the second synchronization determination means that determines the synchronization state based on the presence or absence thereof, and the first synchronization determination means and the second synchronization determination means is calculated, and the determination result of the synchronization state is output. A synchronization determination circuit, comprising: 2. A synchronization determination circuit of a television receiver, wherein first synchronization determination means detects a horizontal synchronization signal from a received signal and determines a synchronization state based on the presence / absence thereof, and a frame synchronization signal from the received signal. Second synchronization determination means for determining the synchronization state based on the presence or absence thereof, C / N detection means for detecting the noise amount according to the received C / N from the received signal, and noise detected by the C / N detection means. A synchronization determination circuit comprising: switching means for selectively outputting the outputs of the two synchronization determination circuits according to the amount. 3. A synchronization determination circuit of a television receiver, wherein first synchronization determination means detects a horizontal synchronization signal from a received signal and determines a synchronization state based on the presence or absence thereof, and a frame synchronization signal from the received signal. Then, the determination result derived from the second synchronization determination means that determines the synchronization state based on the presence or absence thereof, and the first synchronization determination means and the second synchronization determination means is calculated, and the determination result of the synchronization state is output. Switching means for switching the arithmetic method in the arithmetic means according to the noise amount detected by the C / N detecting means and the noise amount detected by the C / N detecting means. Means, frame synchronization determination means for determining frame synchronization loss when frame synchronization is not detected for a predetermined period, and whether the input signal is a broadcast signal or VDP (Video disc player) and V
A control signal input terminal for inputting a discrimination signal capable of discriminating whether or not the signal is from a package medium such as a TR (video tape recorder), and the arithmetic means in accordance with the discrimination signal input from the control signal input terminal. A synchronization determination circuit comprising an output and a switching means for selecting an output from the frame synchronization determination means. 4. A synchronization determination circuit of a television receiver, wherein first synchronization determination means detects a horizontal synchronization signal from a received signal and determines a synchronization state from the presence or absence of the horizontal synchronization signal, and a frame synchronization signal from the received signal. Then, the determination result derived from the second synchronization determination means that determines the synchronization state based on the presence or absence thereof, and the first synchronization determination means and the second synchronization determination means is calculated, and the determination result of the synchronization state is output. Switching means for switching the arithmetic method in the arithmetic means according to the noise amount detected by the C / N detecting means and the noise amount detected by the C / N detecting means. Means, frame synchronization determination means for determining frame synchronization loss when frame synchronization is not detected for a predetermined period, and whether the input signal is a broadcast signal or VDP (Video disc player) and V
A control signal input terminal for inputting a discrimination signal capable of discriminating whether the signal is from a package medium such as a TR (video tape recorder), and the output of the computing means in response to the discrimination signal input from the control signal input terminal. A synchronization determination circuit comprising: a second switching means for selecting the presence / absence of the signal; and a second computation means for computing the synchronization state from the output of the computation means and the output of the frame synchronization determination means.