JPH0595297A - Noise canceller - Google Patents

Abstract

PURPOSE:To reduce mis-recognition of a regular pulse as an irregular pulse due to noise in the regular pulse by outputting a pulse detection signal from a comparison means based on a front edge detection signal and a pulse trailing edge confirming signal. CONSTITUTION:Pulse front edge detection means 1-3 detect a pulse front edge of an input signal and output a front edge detection signal after a prescribed time (e.g. 2mus). Moreover, pulse trailing edge confirming means 4, 6, 7, 8 detect a pulse trailing edge of the input signal to detect whether or not there is a change in the input signal within a prescribed time (e.g. 0.6mus) from that point of time. When any change is in existence, the trailing edge is neglected and when no change is in existence, a pulse trailing edge confirming signal is outputted. Then comparator means 5 outputs a pulse detection signal based on the front edge detection signal outputted from the means 1-3 and the pulse trailing edge confirming signal outputted from the means 4, 6, 7, 8. Thus, mis- recognition of a regular pulse as an irregular pulse due to noise in existence in the regular pulse is reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a noise canceller used in descramble processing of a CATV (cable television) system.

[0002]

2. Description of the Related Art In recent years, large-scale CATV systems that provide a variety of advanced services such as high image quality and multiple channels are rapidly becoming widespread. Among them, pay service programs such as movies and sports programs are increasing, and non-contractors are scrambled so that the pay programs cannot be viewed.

As a scramble system of the CATV system, there is a synchronous compression system, which compresses horizontal and vertical synchronizing signals of a video signal to a constant level on the transmitting side and compresses it based on key data transmitted simultaneously on the receiving side. This is a method of expanding the portion that has been restored to the original level and restoring it to a normal television signal.

In some cases, the compressed horizontal / vertical synchronizing signals are synchronously separated and used as timing pulses for generating a clamp pulse for direct current reproduction of a descramble signal.

Normally, the scrambled signal input to the receiving terminal of the CATV system has various noise levels depending on the distance from the center to the receiving terminal, and a noise canceller after synchronization separation is used so as not to be affected by noise.

FIG. 3 shows an example of a conventional noise canceller. In FIG. 3, reference numeral 1 denotes a pulse leading edge detection circuit that detects a pulse leading edge by detecting a level change of an input signal such as a sync separation signal. Reference numeral 2 is a flip-flop set by the output of the pulse leading edge detection circuit 1. A counter 3 is activated when the flip-flop 2 is set and outputs an enable signal which is a leading edge detection signal after a predetermined time e.g. 2 μS in the case of a sync separation signal based on a clock signal. Four
Is a pulse trailing edge detection circuit that is activated when the flip-flop 2 is set, detects the pulse trailing edge of the input signal, and outputs a pulse trailing edge detection signal.

Reference numeral 5 is a timing comparison circuit for comparing the timing of the enable signal output by the counter 3 and the timing of the pulse trailing edge detection signal output by the pulse trailing edge detection circuit 4. When the pulse trailing edge detection signal is input before the enable signal is input, the timing comparison circuit 5 determines that there is noise, resets the flip-flop 2 and the counter 3, and after the enable signal is input. When the pulse trailing edge detection signal is input, it is determined that the pulse is a signal pulse, and the pulse detection signal is output.

The operation of the noise canceller configured as described above will be described below.

FIG. 4 is an operation timing chart when a regular pulse signal is input. FIG. 4A shows an input signal such as a sync separation signal, and the pulse leading edge detection circuit 1
The pulse leading edge signal (b) is output. The pulse width of the input signal (a) is, for example, about 4.7 μS in the case of the horizontal sync separation signal. The flip-flop 2 is set by the pulse leading edge signal (b), and the set signal (c) is output. Next, the counter 3 is activated by the set signal (c), the counting operation is started by the clock signal, and the enable signal (d) is output after a predetermined time, for example, 2 μS. At the same time, the pulse trailing edge detection circuit 4 and the timing comparison circuit 5 are activated by the set signal (c). After that, the pulse trailing edge detection circuit 4 detects the pulse trailing edge of the input signal (a) and outputs the pulse trailing edge detection signal (e) to the timing comparison circuit 5. In this case, since the pulse trailing edge detection signal (e) is output after the enable signal (d) is input, the timing comparison circuit 5 outputs the pulse trailing edge portion at the time when the enable signal (d) is input. The detection signal (e) is input, and it is determined that the pulse signal is a regular pulse signal, and the pulse detection signal (f) is output. After outputting the pulse detection signal (f), the timing comparison circuit 5 resets the flip-flop 2 and the counter 3 so that the next input signal can be detected.

FIG. 5 is an operation timing chart of a conventional noise canceller when an irregular pulse, for example, a noise pulse having a pulse width of 2 μS or less is input as an input signal. FIG. 5A shows an input noise signal. The input noise signal (a) causes the pulse leading edge detection circuit 1 to output the pulse leading edge signal (b), and the flip-flop 2 is set. (C) is output. Next, the counter 3 is activated by the set signal (c), and the counting operation is started by the clock signal. At the same time, the pulse trailing edge detection circuit 4 and the timing comparison circuit 5 are activated by the set signal (c). After that, the pulse trailing edge detection circuit 4 detects the pulse trailing edge of the input noise signal (a) and outputs the pulse trailing edge detection signal (e) to the timing comparison circuit 5. In this case, since the pulse trailing edge detection signal (e) is output before the enable signal (d) is input, the timing comparison circuit 5 causes the pulse trailing edge to be detected when the enable signal (d) is not input. When the copy detection signal (e) is input, it is determined that there is noise, and the flip-flop 2 and the counter 3 are reset. The pulse detection signal (f) is not output from the timing comparison circuit 5, and the irregular pulse input signal is excluded.

[0011]

However, as described above, in the conventional noise canceller, a pulse generated in the interval time between pulses and having a width smaller than the enable time width can be eliminated as noise. Two
When noise is present in the pulse of the regular input signal as shown in (a), the leading edge of the noise is regarded as the trailing edge of the pulse, and the time from the leading edge of the pulse to the noise is defined as the pulse time width. If the pulse width is checked and the pulse width is equal to or shorter than the enable time, there is a problem that even a regular pulse is excluded as noise.

The present invention has been made in consideration of the above-mentioned conventional problems,
It is an object of the present invention to provide a noise canceller in which a regular pulse is less likely to be erroneously recognized as an irregular pulse due to noise existing in the regular pulse.

[0013]

According to the present invention, there is provided a pulse leading edge detecting means for detecting a leading edge portion of a pulse of an input signal and outputting a leading edge detecting signal after a first predetermined time, and a pulse of the input signal. The trailing edge is detected, and it is detected whether or not there is a change in the input signal substantially within the second predetermined time from the detection time. If there is, the trailing edge is ignored, and if not, the pulse trailing edge confirmation signal is detected. A pulse detection signal is output based on the output pulse trailing edge confirmation means, the leading edge detection signal output by the pulse leading edge detection means, and the pulse trailing edge confirmation signal output by the pulse trailing edge confirmation means. It is a noise canceller equipped with a comparison means.

[0014]

According to the present invention, the pulse leading edge detection means detects the pulse leading edge portion of the input signal, outputs the leading edge detection signal after the first predetermined time, and the pulse trailing edge confirmation means inputs the pulse leading edge detection signal. Detecting the pulse trailing edge of the signal, detecting whether there is a substantial change in the input signal within the second predetermined time from the time of detection, ignoring the trailing edge if any, trailing pulse if not A confirmation signal is output, and the comparison means outputs a pulse detection signal based on the leading edge detection signal output by the pulse leading edge detection means and the pulse trailing edge confirmation signal output by the pulse trailing edge confirmation means.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings showing its embodiments.

FIG. 1 is a block diagram of a noise canceller according to an embodiment of the present invention. That is, the pulse front edge detection circuit 1 for detecting the pulse front edge of the input signal is connected to the first flip-flop 2 set by the pulse front edge signal detecting the pulse front edge. The first flip-flop 2 is connected to a first counter 3 which is activated by the set signal of the first flip-flop 2 and outputs an enable signal which is a leading edge detection signal after a first predetermined time, for example, 2 μS. .. The pulse leading edge detection circuit 1, the first flip-flop 2,
The first counter 3 constitutes the pulse leading edge detecting means.

Separately, there is provided a pulse trailing edge detection circuit 4 which is activated by the set signal of the first flip-flop 2 and detects the pulse trailing edge portion of the input signal. The second flip-flop 6 set by the signal detecting the trailing edge of the pulse is connected,
The second flip-flop 6 is provided with a second counter 7 which is activated by the set signal of the second flip-flop 6 and outputs an enable signal which is a pulse trailing edge detection signal after a second predetermined time, for example, 0.6 μS. The second counter 7 is connected, detects a level change of the input signal, and is activated by the set signal of the second flip-flop 6,
A pulse trailing edge confirmation circuit 8 for confirming whether the pulse is a regular pulse trailing edge is connected. The pulse trailing edge confirmation circuit 8 includes a second flip-flop 6 and a second counter 7.
Connected to them so that they can be reset. The pulse trailing edge detection circuit 4, the second flip-flop 6,
The second counter 7 and the pulse trailing edge confirmation circuit 8 constitute pulse trailing edge confirmation means.

The above-mentioned first counter 3 and pulse trailing edge confirmation circuit 8 are activated by the set signal of the first flip-flop 2 and output to the enable signal and pulse trailing edge confirmation circuit of the first counter 3. A timing comparison circuit 5 as a comparison means is connected to compare the pulse trailing edge confirmation signals output by 8 and output a pulse detection signal based on the result. The timing comparison circuit 5 is connected to the first flip-flop 2 and the first counter 3 so that they can be reset.

Further, the first counter 3 and the second counter 7
To output the enable signal delayed by a predetermined time,
A clock signal is being input.

Next, the operation of the above embodiment will be described.

FIG. 2 is an operation timing chart when noise is present in the normal pulse signal. First, when each circuit is in a reset state, an input signal is input. It is assumed that the input signal (a) has noise of a minute pulse having a pulse width of 0.6 μS or less in a regular signal pulse. The pulse leading edge detection circuit 1 detects the pulse leading edge,
The pulse leading edge signal (b) is output to the first flip-flop 2. The first flip-flop 2 outputs the set signal (c) in response to the pulse leading edge signal (b), and activates the first counter 3, the timing comparison circuit 5, and the pulse trailing edge detection circuit 4. After that, after 2 μS of the first predetermined time, the enable signal (d) is output from the first counter 3 to the timing comparison circuit 5.

On the other hand, the pulse trailing edge detection circuit 4 regards the leading edge of the noise in the pulse as the pulse trailing edge and outputs the pulse trailing edge detection signal (e). The second flip-flop 6 is set by the pulse trailing edge detection signal (e), and the second counter 7 and the pulse trailing edge confirmation circuit 8 are activated by the set signal. In this case, since the noise pulse has a pulse width of 0.6 μS or less, the level of the input signal returns to the signal pulse before the second counter 7 outputs the enable signal with a delay of 0.6 μS of the second predetermined time. As a result, the pulse trailing edge confirmation circuit 8 resets the second flip-flop 6 and the second counter 7, and ignores this noise pulse. After that, when the pulse trailing edge detection circuit 4 detects the trailing edge of the normal signal pulse, the second flip-flop 6 is set by the pulse trailing edge detection signal (e) and the set signal ( The second counter 7 and the like are activated by f). This time the second counter 7
Has output the enable signal (g) after a delay of 0.6 μS of the second predetermined time, the level of the input signal remains unchanged, so the pulse trailing edge confirmation circuit 8 outputs the pulse trailing edge confirmation signal (h). Is output. Since the enable signal (d) is output to the timing comparison circuit 5 from the first counter 3 with a delay of 2 μS as described above, the normal signal pulse is compared with the pulse trailing edge confirmation signal (g). The pulse detection signal is output by determining that it is the trailing edge.

In the above embodiment, the first predetermined time is 2
μS and the second predetermined time are set to 0.6 μS, but the present invention is not limited to this, and may be set to another time depending on the quality of noise.

[0024]

As is apparent from the above description, the present invention provides a pulse leading edge detecting means for detecting a pulse leading edge of an input signal and outputting a leading edge detecting signal after a first predetermined time. , Detecting the trailing edge of the pulse of the input signal, detecting whether there is substantially no change in the input signal within the second predetermined time from the time of detection, ignoring the trailing edge if any, and after the pulse if not Based on the pulse trailing edge confirmation means for outputting the edge confirmation signal, the leading edge detection signal output by the pulse leading edge detection means and the pulse trailing edge confirmation signal output by the pulse trailing edge confirmation means Since the comparison means for outputting the detection signal is provided, there is an advantage that the normal pulse is less likely to be erroneously recognized as an irregular pulse due to noise existing in the regular pulse.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a noise canceller according to an embodiment of the present invention.

FIG. 2 is a timing diagram of a noise canceller in an embodiment of the present invention when noise is present in a regular pulse.

FIG. 3 is a configuration diagram of a conventional noise canceller.

FIG. 4 is an operation timing chart of a conventional noise canceller when a regular pulse is input.

FIG. 5 is an operation timing chart of a conventional noise canceller when an irregular pulse is input.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 pulse leading edge detection circuit 2 1st flip-flop 3 1st counter 4 pulse trailing edge detection circuit 5 timing comparison circuit 6 2nd flip-flop 7 2nd counter 8 pulse trailing edge confirmation circuit

Claims (1)

[Claims] 1. A pulse leading edge detecting means for detecting a pulse leading edge of an input signal and outputting a leading edge detecting signal after a first predetermined time, and detecting a pulse trailing edge of the input signal, A pulse for detecting whether or not there is substantially a change in the input signal within a second predetermined time from the detection time point, and ignoring the detected trailing edge portion if there is any, and outputting a pulse trailing edge portion confirmation signal if not. A pulse detection signal is output based on the trailing edge confirmation means, the leading edge detection signal output by the pulse leading edge detection means, and the pulse trailing edge confirmation signal output by the pulse trailing edge confirmation means. A noise canceller characterized by comprising: