KR910016069A - Lead frame and semiconductor device - Google Patents

Lead frame and semiconductor device Download PDF

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Publication number
KR910016069A
KR910016069A KR1019900014537A KR900014537A KR910016069A KR 910016069 A KR910016069 A KR 910016069A KR 1019900014537 A KR1019900014537 A KR 1019900014537A KR 900014537 A KR900014537 A KR 900014537A KR 910016069 A KR910016069 A KR 910016069A
Authority
KR
South Korea
Prior art keywords
plane
lead frame
semiconductor device
metal plane
inner lead
Prior art date
Application number
KR1019900014537A
Other languages
Korean (ko)
Other versions
KR930004253B1 (en
Inventor
미쓰하루 시미즈
요시끼 다께다
히로후미 후지
Original Assignee
이노우에 사다오
신고오 덴기 고오교오 가부시끼가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP2026786A external-priority patent/JP2784235B2/en
Application filed by 이노우에 사다오, 신고오 덴기 고오교오 가부시끼가이샤 filed Critical 이노우에 사다오
Publication of KR910016069A publication Critical patent/KR910016069A/en
Application granted granted Critical
Publication of KR930004253B1 publication Critical patent/KR930004253B1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

내용 없음No content

Description

리드프레임 및 반도체장치Lead frame and semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명에 의한 반도체장치의 일실시예를 나타낸 단면도, 제2도는 반도체장치에 사용되는 리드프레임의 저면도, 제3도는 와이어 본딩 영역등을 확대시켜 나타낸 설명도.1 is a cross-sectional view showing an embodiment of a semiconductor device according to the present invention, FIG. 2 is a bottom view of a lead frame used in a semiconductor device, and FIG. 3 is an explanatory view showing an enlarged wire bonding area or the like.

Claims (3)

인너리드에 전원플레인 및/또는 접지 플레인으로서 별개체로 형성한 금속플레인을 절연층을 거쳐서 접합한 다층 리드프레임에 있어서, 상기 금속플레인의 와이어 본딩영역을 사이에 끼운 양측 또는 편측에 투공을 설비한 것을 특징으로 하는 리드프레임.In a multi-layered lead frame in which an inner lead is bonded to a metal plane formed as a separate power supply plane and / or a ground plane via an insulating layer, a perforation is provided on both sides or one side between the wire bonding regions of the metal plane. Lead frame, characterized in that. 인너리드에 전원플레인 및/또는 접지플레인으로서 별개체로 형성한 금속플레인을 절연층을 거쳐서 접합한 다층 리드프레임에 반도체 칩을 탑재하고 인너리드 및 금속플레인과 반도체 칩과의 사이를 와이어 본딩하고 수지봉지된 수지통지형 반도체장치에 있어서, 상기 금속플레인의 와이어 본딩영역을 사이에 끼운 양측 또는 그 편측에 투공이 형성되고 이 투공에상기 봉지수지가 채워져 있는 것을 특징으로 하는 반도체장치.A semiconductor chip is mounted on a multi-layered lead frame in which an independent metal plane formed as an power plane and / or a ground plane is bonded to an inner lead through an insulating layer, and wire bonding between the inner lead and the metal plane and the semiconductor chip is performed. A sealed resin-type semiconductor device, comprising: perforations formed on both sides or one side thereof sandwiching a wire bonding region of the metal plane, and the encapsulating resin is filled in the perforations. 제2항에 있어서, 상기 인너리드의 하면과 대향하는 금속플레인 및 절연층부에 관통공이 설비되고 이 관통공에도 봉지수지가 채워져 있는 것을 특징으로 하는 반도체장치.The semiconductor device according to claim 2, wherein a through hole is provided in the metal plane and the insulating layer facing the lower surface of the inner lead, and the sealing resin is filled in the through hole. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019900014537A 1990-02-06 1990-09-14 Rid-frame and semiconductor device KR930004253B1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP26786/2 1990-02-06
JP2026786A JP2784235B2 (en) 1989-10-16 1990-02-06 Lead frame and semiconductor device
JP2-26786 1990-02-06

Publications (2)

Publication Number Publication Date
KR910016069A true KR910016069A (en) 1991-09-30
KR930004253B1 KR930004253B1 (en) 1993-05-22

Family

ID=12203000

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019900014537A KR930004253B1 (en) 1990-02-06 1990-09-14 Rid-frame and semiconductor device

Country Status (1)

Country Link
KR (1) KR930004253B1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100342812B1 (en) * 1996-11-28 2002-11-18 앰코 테크놀로지 코리아 주식회사 Area array bumped semiconductor package having ground and power lines
KR100533750B1 (en) * 2000-07-13 2005-12-06 앰코 테크놀로지 코리아 주식회사 Lead Frame Used for the Fabrication of Semiconductor Package and Semiconductor Package Fabricated Using the Same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100342812B1 (en) * 1996-11-28 2002-11-18 앰코 테크놀로지 코리아 주식회사 Area array bumped semiconductor package having ground and power lines
KR100533750B1 (en) * 2000-07-13 2005-12-06 앰코 테크놀로지 코리아 주식회사 Lead Frame Used for the Fabrication of Semiconductor Package and Semiconductor Package Fabricated Using the Same

Also Published As

Publication number Publication date
KR930004253B1 (en) 1993-05-22

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