KR910016071A - Resin Sealed Semiconductor Device - Google Patents

Resin Sealed Semiconductor Device Download PDF

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Publication number
KR910016071A
KR910016071A KR1019910002059A KR910002059A KR910016071A KR 910016071 A KR910016071 A KR 910016071A KR 1019910002059 A KR1019910002059 A KR 1019910002059A KR 910002059 A KR910002059 A KR 910002059A KR 910016071 A KR910016071 A KR 910016071A
Authority
KR
South Korea
Prior art keywords
resin
depth
semiconductor device
chip
semiconductor chip
Prior art date
Application number
KR1019910002059A
Other languages
Korean (ko)
Other versions
KR940007378B1 (en
Inventor
가즈히토 고바야시
Original Assignee
아오이 죠이치
가부시키가이샤 도시바
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 아오이 죠이치, 가부시키가이샤 도시바 filed Critical 아오이 죠이치
Publication of KR910016071A publication Critical patent/KR910016071A/en
Application granted granted Critical
Publication of KR940007378B1 publication Critical patent/KR940007378B1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

내용 없음No content

Description

수지밀봉형 반도체장치Resin Sealed Semiconductor Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명에 따른 1실시예의 요부확대단면도, 제2도는 본 발명에 따른 1실시예의 전체단면도, 제3도는 본 발명에 따른 1실시예의 리드프레임의 요부평면도.1 is an enlarged sectional view of a main part of an embodiment according to the present invention, FIG. 2 is a whole sectional view of an embodiment according to the present invention, and FIG. 3 is a main plan view of a lead frame of an embodiment according to the present invention.

Claims (2)

상면에 반도체칩(3)을 탑재한 칩탑재부(1a)의 하면으로부터 패키지하면 까지의 하측매설깊이(S2)와 상기 반도체칩의 상면으로부터 패키지상면까지의 상측매설깊이(S1)가 다르게 되어 있는 수지밀봉형 반도체장치에 있어서, 이 양깊이중 보다 깊은 쪽에 인접한 리드프레임(1)의 내부리드(1b)의 표면에 이 내부리드매설부에서의 수지에 의한 상측매설깊이를 변화시켜 패키지에 휨을 발생시키기 위한 판형상의 절연체(7)를 배치한 것을 특징으로 하는 수지밀봉형 반도체장치.The lower embedding depth S 2 from the lower surface of the chip mounting portion 1a on which the semiconductor chip 3 is mounted on the upper surface to the lower surface of the chip is different from the upper embedding depth S 1 from the upper surface of the semiconductor chip to the upper surface of the package. In the resin-sealed semiconductor device in which the depth is deeper, the depth of the upper buried depth by the resin in the inner lead embedding portion is changed on the surface of the inner lead 1b of the lead frame 1 adjacent to the deeper one of the two depths. A resin-sealed semiconductor device comprising a plate-shaped insulator (7) for generation. 상면에 반도체칩(3)을 탑재한 칩탑재부(1a,1a')의 하면으로부터 패키지하면까지의 하측매설깊이와 상기 반도체칩의 상면으로부터 패키지상면까지의 상측매설깊이(S1,S1")가 다르게 되어 있는 수지밀봉형 반도체장치에 있어서, 상기 칩탑재부하면 또는 반도체칩 상면에 상기 반도체칩 매설부에 있어서의 수지에 의한 상하매설깊이를 거의 작아지게 하기 위한 절연체(8,9)를 배치한 것을 특징으로 하는 수지밀봉형 반도체장치.Lower buried depth from the lower surface of the chip mounting portion 1a, 1a 'on which the semiconductor chip 3 is mounted on the upper surface to the lower surface of the package, and the upper buried depth from the upper surface of the semiconductor chip to the upper surface of the package (S 1 , S 1 "). In the resin-sealed semiconductor device having a different shape, an insulator (8, 9) is disposed on the chip mounting portion or on the upper surface of the semiconductor chip to substantially reduce the depth of vertical filling by the resin in the semiconductor chip embedding portion. Resin-sealed semiconductor device, characterized in that. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019910002059A 1990-02-07 1991-02-07 Resin-sealed semiconductor device KR940007378B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP02-028015 1990-02-07
JP2028015A JP2531817B2 (en) 1990-02-07 1990-02-07 Resin-sealed semiconductor device

Publications (2)

Publication Number Publication Date
KR910016071A true KR910016071A (en) 1991-09-30
KR940007378B1 KR940007378B1 (en) 1994-08-16

Family

ID=12236942

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910002059A KR940007378B1 (en) 1990-02-07 1991-02-07 Resin-sealed semiconductor device

Country Status (2)

Country Link
JP (1) JP2531817B2 (en)
KR (1) KR940007378B1 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6388338B1 (en) * 1995-04-28 2002-05-14 Stmicroelectronics Plastic package for an integrated electronic semiconductor device
JP5256128B2 (en) * 2009-06-18 2013-08-07 日立オートモティブシステムズ株式会社 Electronic circuit enclosure

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58191457A (en) * 1982-05-04 1983-11-08 Toshiba Corp Semiconductor device
JPS61207038A (en) * 1985-03-11 1986-09-13 Fujitsu Ltd Resin sealed type semiconductor device
JPH0519958Y2 (en) * 1985-08-20 1993-05-25
JPS6352451A (en) * 1986-08-22 1988-03-05 Hitachi Vlsi Eng Corp Resin-sealed semiconductor device
EP0261324A1 (en) * 1986-09-26 1988-03-30 Texas Instruments Incorporated Plastic package for large chip size integrated circuit

Also Published As

Publication number Publication date
JP2531817B2 (en) 1996-09-04
KR940007378B1 (en) 1994-08-16
JPH03232257A (en) 1991-10-16

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