KR910009741B1 - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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KR910009741B1
KR910009741B1 KR1019880005992A KR880005992A KR910009741B1 KR 910009741 B1 KR910009741 B1 KR 910009741B1 KR 1019880005992 A KR1019880005992 A KR 1019880005992A KR 880005992 A KR880005992 A KR 880005992A KR 910009741 B1 KR910009741 B1 KR 910009741B1
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silicon
oxide film
silicon oxide
film
forming
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KR890017816A (en
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이앙구
유재안
한민석
김석식
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삼성전자 주식회사
김광호
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors

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Abstract

The semiconductor device for improving the charge transport efficiency is manufactured by; forming a first silicon oxide film (2), a first silicon nitride film (6), a first polycrystal line silicon layer (3) and a second silicon oxide film (7), in sequence on silicon substrate (1); depositing a photoresist (8) on (7), followed by etching with photolithography process; removing the photoresist, followed by forming a second silicon nitride film (9) and a third silicon oxide film (10) on (2) and (7); forming a space by dry etching the (9) and (10); forming a second polycrystal line silicon layer (5).

Description

반도체 장치의 제조 방법Manufacturing Method of Semiconductor Device

제1도는 종래의 스페이스를 사용한 CCD의 단면도.1 is a cross-sectional view of a CCD using a conventional space.

제2a-e도는 본 발명의 실시예를 보인 CCD의 제조 공정도이다.2a-e is a manufacturing process diagram of a CCD showing an embodiment of the present invention.

이 발명은 반도체 장치의 제조 방법에 관한 것으로, 특히 전하 결합 소자에 있어서 제1 다결정 실리콘층의 측벽에 형성되는 스페이스 폭을 최소화하고 제2 다결정 실리콘층의 형성전에 게이트 산화규소막을 형성할 때 발생되는 제1 다결정 실리콘의 산화 현상을 억제시키기 위해 제1 다결정 실리콘층을 형성하기 전에 질화규소막을 형성하는 반도체 장치의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and in particular, in a charge coupled device, which is generated when the gate silicon film is formed before minimizing the space width formed on the sidewall of the first polycrystalline silicon layer and forming the second polycrystalline silicon layer. A method of manufacturing a semiconductor device in which a silicon nitride film is formed before forming a first polycrystalline silicon layer to suppress oxidation of the first polycrystalline silicon.

제1도는 종래의 전하 결합 소자(charge coupled device, 이하 CCD라 함)의 단면도를 도시한 것이다.1 is a cross-sectional view of a conventional charge coupled device (hereinafter referred to as a CCD).

제1도의 단면도에 나타낸 바와 같이 반도체기판(1) 위에 불순물을 도핑시킨 제1 다결정 실리콘층(3)과 제2 다결정 실리콘층(5)이 형성되는데, 이들 층간의 절연막으로서 얇은 산화규소막(2, 4)으로 격리시켰다. 이와 같이 형성되는 종래의 CCD는 산화규소막(4)을 형성할 때, 고농도로 불순물이 주입되어 있는 제1 다결정 실리콘층(3)의 산화현상이 발생하여 제1 다결정 실리콘층(3)의 코너부분(e1, e2)이 산화규소막(4)보다 약 2∼3배 정도의 빠른 산화가 일어나서 산화규소막이 두껍게 형성되기 때문에 CCD의 전하 전송 효율(charge transfer efficiency)이 저하되는 문제점이 있었다.As shown in the cross-sectional view of FIG. 1, a first polycrystalline silicon layer 3 and a second polycrystalline silicon layer 5 doped with impurities are formed on the semiconductor substrate 1, and a thin silicon oxide film 2 as an insulating film between these layers is formed. , 4). In the conventional CCD formed as described above, when the silicon oxide film 4 is formed, oxidation of the first polycrystalline silicon layer 3 into which impurities are injected at a high concentration occurs so that the corner of the first polycrystalline silicon layer 3 is formed. Since the portions e 1 and e 2 are oxidized about two to three times faster than the silicon oxide film 4, and the silicon oxide film is formed thick, the charge transfer efficiency of the CCD is lowered. .

또한, 제1 및 제2 다결정 실리콘층(3) (5)을 격리시키기 위한 산화규소막(2, 4)의 측벽의 폭 즉, 스페이스(S)가 두껍게 형성되어 전송효율이 감소되는 문제점이 있었다.In addition, the width of the sidewalls of the silicon oxide films 2 and 4 for isolating the first and second polycrystalline silicon layers 3 and 5, that is, the space S is formed thick, has a problem in that the transmission efficiency is reduced. .

이 발명의 목적은 제1 다결정 실리콘층의 측벽에 형성된 스페이스의 폭을 최소화하고 다결정 실리콘층 하부의 산화 규소막 형성시 발생하는 제1 다결정 실리콘층의 산화현상을 억제시켜 소자의 전하 전송 효율을 높일 수 있는 반도체 장치의 제조 방법을 제공하는데 있다.An object of the present invention is to minimize the width of the space formed on the sidewall of the first polycrystalline silicon layer and to increase the charge transfer efficiency of the device by suppressing the oxidation of the first polycrystalline silicon layer generated when forming the silicon oxide film under the polycrystalline silicon layer. It is to provide a method for manufacturing a semiconductor device that can be.

이와 같은 목적을 달성하기 위한 이 발명은 실리콘 기판 위에 제1 산화규소막 제1 질화규소막, 제1 다결정 실리콘층, 제2 산화규소막을 순차적으로 형성하는 공정과, 상기 제2 산화규소막 위에 감광액을 도포한 다음 사진식각공정으로 소정의 패턴을 가진 마스크를 사용하여 에칭시키는 공정과, 상기 감광액을 제거하고 상기 제1 산화규소막 및 제2 산화규소막 위에 제9 질화규소막, 제3 산화규소막을 순차적으로 형성하는 공정과, 전면식각법으로 상기 제2 질화규소막 및 제3 산화규소막을 드라이 에칭하여 제1 다결정 실리콘의 측벽 부에 스페이스를 형성하는 공정과, 제1 산화규소막을 키우고 제2 다결정 실리콘을 형성하는 공정으로 이루어진 것을 특징으로 한다.In order to achieve the above object, the present invention provides a method of sequentially forming a first silicon oxide film, a first silicon nitride film, a first polycrystalline silicon layer, and a second silicon oxide film on a silicon substrate, and a photoresist on the second silicon oxide film. Applying and then etching using a mask having a predetermined pattern by a photolithography process; and removing the photoresist and sequentially forming a ninth silicon nitride film and a third silicon oxide film on the first silicon oxide film and the second silicon oxide film. Forming a space in the sidewall portion of the first polycrystalline silicon by dry etching the second silicon nitride film and the third silicon oxide film by a front etching method, and growing the first silicon oxide film and It is characterized by consisting of a step of forming.

이하, 첨부된 도면을 참조하여 이 발명의 바람직한 실시예를 상세히 설명한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

제2a도 내지 제2e도는 이 발명의 제조 공정도를 나타낸 것이다. 이 공정도에 나타낸 바와 같이 실리콘 기판(1)위에 제1 산화규소막(2)을 1000Å정도의 두께로 형성한 다음 제1 질화규소막(6)을 100Å정도의 두께로 얇게 형성시키고, 제1 다결정 실리콘(3)과 제1 산화규소막(7)을 순차적으로 형성시키면 제2a도와 같이 된다.2a to 2e show a manufacturing process diagram of the present invention. As shown in this process chart, the first silicon oxide film 2 is formed on the silicon substrate 1 to a thickness of about 1000 mW, and then the first silicon nitride film 6 is formed to be thin to about 100 mW, and the first polycrystalline silicon is formed. (3) and the first silicon oxide film 7 are sequentially formed as shown in FIG. 2A.

이때, 제1 질화규소막(6)은 제1도에서처럼 산화규소막(4) 위에 제1 다결정실리콘(3)을 형성할때 제1 다결정 실리콘층(3)의 코너부분(e1, e2)이 열산화되는 것을 방지하기 위해 형성한 것이다.At this time, the first silicon nitride film 6 forms corners e 1 and e 2 of the first polycrystalline silicon layer 3 when the first polycrystalline silicon 3 is formed on the silicon oxide film 4 as shown in FIG. 1. It is formed to prevent thermal oxidation.

이와 같이 제2 산화규소막(2), 제1 질화규소막(6), 제1 다결정 실리콘층(3) 및 제2 산화규소막(7)을 순차적으로 형성한 다음, 감광액(Photoresist, 8)을 도포하고 사진 식각 공정을 하여 제2b도와 같이 패턴을 형성한다.As such, the second silicon oxide film 2, the first silicon nitride film 6, the first polycrystalline silicon layer 3, and the second silicon oxide film 7 are sequentially formed, and then the photoresist 8 is formed. A pattern is formed by applying and performing a photolithography process as shown in FIG. 2B.

패턴을 형성한 후 감광액(8)을 제거하고, 제2 질화규소막(9)을 100Å정도의 두께로 얇게 침적한 후, 제3산화규소막(10)을 침적시키면 제2c도와 같이 된다After the pattern is formed, the photosensitive liquid 8 is removed, and the second silicon nitride film 9 is thinly deposited to a thickness of about 100 GPa, and then the third silicon oxide film 10 is deposited to have a degree of 2c.

따라서, 제1 다결정 실리콘층(3) 및 제2 산화규소막(7)의 전면이 제1, 제2질화규소막(6) (9)으로 에워싸이게 된다.Thus, the entire surface of the first polycrystalline silicon layer 3 and the second silicon oxide film 7 is surrounded by the first and second silicon nitride films 6 and 9.

제2 산화규소막(10)을 침적시킨 다음, 제1 다결정 실리콘층(3)의 측벽을 제외한 제2 질화규소막(9)과 제3 산화규소막(10)을 전면건식식각법을 사용하여 에칭시킨다. 이때, 패턴 형성부의 제2 산화규소막(7) 및 제1 산화규소막(2)의 일부분이 드러나게 건식 에칭 시간을 충분히 크게 하여 제1 산화규소막(2)의 두께가 100Å정도가 남게 건식 에칭한 다음, 나머지는 습식에칭(Wetetching)을 하여 실리콘 기판이 손상되지 않도록 한다. 이 공정이 끝나면 제2d도와 같은 스페이스(S)가 형성된다. 이렇게 형성되는 스페이스(S)의 폭은 1500Å∼1700Å 정도로 얇게 형성한다. 이어서 제2 산화규소막(2)을 선택적으로 열산화시켜 키우고, 제2 다결정 실리콘층(5)을 형성하면 제2e도와 같이 되어 이 발명의 반도체 장치가 완성된다.After the second silicon oxide film 10 is deposited, the second silicon nitride film 9 and the third silicon oxide film 10 except for the sidewalls of the first polycrystalline silicon layer 3 are etched by using a dry etching method. Let's do it. At this time, the dry etching time is sufficiently large so that the portions of the second silicon oxide film 7 and the first silicon oxide film 2 of the pattern forming portion are exposed, and the dry etching is performed such that the thickness of the first silicon oxide film 2 remains about 100 μs. Then, the rest is wet etched to prevent damage to the silicon substrate. After this process, a space S as shown in FIG. 2d is formed. The width of the space S formed as described above is formed to be as thin as 1500 kPa to 1700 kPa. Subsequently, the second silicon oxide film 2 is selectively thermally oxidized, and the second polycrystalline silicon layer 5 is formed, as shown in FIG. 2E to complete the semiconductor device of the present invention.

이와 같이 이 발명은 산화규소막과 다결정 실리콘층 사이에 질화규소막을 형성시켜 다결정 실리콘의 산화를 방지함으로써 다결정 실리콘의 전기적 특성이 안정되게 한다. 또한, 제1 산화규소막을 제1 다결정 실리콘층을 형성한 다음 형성함으로써 제1 다결정 실리콘층과 제2 다결정 실리콘층을 다른 전기적 격리막을 형성함 없이 쉽게 격리시킬 수 있다. 이 발명에 의하면, 다결정 실리콘층 측벽의 스페이스를 최화함으로써 소자의 전하전송 효율을 증가시킬 수 있다.As such, the present invention forms a silicon nitride film between the silicon oxide film and the polycrystalline silicon layer to prevent oxidation of the polycrystalline silicon, thereby making the electrical properties of the polycrystalline silicon stable. In addition, by forming the first silicon oxide film after forming the first polycrystalline silicon layer, the first polycrystalline silicon layer and the second polycrystalline silicon layer can be easily isolated without forming another electrical isolation film. According to this invention, the charge transfer efficiency of the device can be increased by minimizing the space of the sidewall of the polycrystalline silicon layer.

Claims (4)

실리콘 기판(1)위에 형성된 제1 및 제8 다결정 실리콘층(3) (5), 사이에 게이트 절연막으로서 산화규소막을 형성하는 반도체 장치의 제조 방법에 있어서, 실리콘 기판(1) 위에 제1산화규소막(2), 제1 질화규소막(6), 제1 다결정 실리콘층(3), 제2 산화규소막(7)을 순차적으로 형성하는 공정과, 상기 제2 산화규소막(7) 위에 감광액(8)을 도포한 다음 사진식각 공정으로 소정의 패턴을 가진 마스크를 사용하여 에칭시키는 공정과, 상기 감광액(8)을 제거하고 상기 제1 산화규소막(2) 및 제2 산화규소막(7) 위에 제2 질화규소막(9) 및, 제3 산화규소막(10)을 순차적으로 형성하는 공정과, 전면식각법으로 상기 제2질화규소막(9) 및 제3 산화규소막(10)을 드라이 에칭하여 스페이스(S)를 형성하는 공정과, 상기 제1 산화규소막(2)을 선택적으로 열산화시켜 키우고 제2 다결정 실리콘층(5)을 형성하는 공정으로 이루어진 것을 특징으로 하는 반도체 장치의 제조 방법.A method of manufacturing a semiconductor device in which a silicon oxide film is formed as a gate insulating film between first and eighth polycrystalline silicon layers 3 and 5 formed on a silicon substrate 1, wherein the first silicon oxide is formed on the silicon substrate 1. Forming a film (2), a first silicon nitride film (6), a first polycrystalline silicon layer (3), and a second silicon oxide film (7) sequentially, and a photoresist (on the second silicon oxide film (7) 8) applying and then etching using a mask having a predetermined pattern by a photolithography process, and removing the photosensitive liquid 8 and the first silicon oxide film 2 and the second silicon oxide film 7 Sequentially forming the second silicon nitride film 9 and the third silicon oxide film 10 thereon, and dry etching the second silicon nitride film 9 and the third silicon oxide film 10 by a front etching method. Forming a space S, and selectively thermally oxidizing the first silicon oxide film 2 to form a second polycrystalline silicide. A method of manufacturing a semiconductor device which is characterized by being a step of forming a layer (5). 제1항에 있어서, 상기 제1 산화규소막(2) 위에 제1 질화규소막(6)을 형성한 다음, 제1 다결정 실리콘층(3)을 형성하여 제1 다결정 실리콘층(3)의 열산화 현상을 방지하는 반도체 장치의 제조 방법.2. The thermal oxidation of the first polycrystalline silicon layer 3 according to claim 1, wherein a first silicon nitride film 6 is formed on the first silicon oxide film 2, and then a first polycrystalline silicon layer 3 is formed. The manufacturing method of the semiconductor device which prevents a phenomenon. 제1항에 있어서, 상기 패턴 형성 후 제2 질화규소막(9)과 제3 산화규소막(10)을 연속으로 침적시켜 제1 다결정 실리콘층(3)의 전면을 질화규소막으로 둘러쌈으로써 제1 및 제2 다결정 실리콘층(3) (5)을 다른 전기적 격리막을 필요로 함 없이 격리시킬 수 있는 것을 특징으로 하는 반도체 장치의 제조 방법.The method of claim 1, wherein after forming the pattern, the second silicon nitride film 9 and the third silicon oxide film 10 are continuously deposited to surround the entire surface of the first polycrystalline silicon layer 3 with the silicon nitride film. And the second polycrystalline silicon layer (3) (5) can be isolated without the need for another electrical isolation film. 제1항에 있어서, 상기 패턴 형성시 연속 침전된 제2 질화규소막(9)과 제3 산화규소막(10)을 제1 다결정 실리콘층(3)의 측벽을 제외하고 전면 식각함으로써 스페이스(S)의 폭을 최소화하는 것을 특징으로 하는 반도체 장치의 제조 방법.The space S of claim 1, wherein the second silicon nitride film 9 and the third silicon oxide film 10 that are continuously precipitated during the pattern formation are etched from the entire surface of the first polycrystalline silicon layer 3 except for the sidewalls of the first polycrystalline silicon layer 3. The method of manufacturing a semiconductor device, characterized in that to minimize the width of the.
KR1019880005992A 1988-05-21 1988-05-21 Manufacturing method of semiconductor device KR910009741B1 (en)

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KR890017816A KR890017816A (en) 1989-12-18
KR910009741B1 true KR910009741B1 (en) 1991-11-29

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