KR910008571A - 2/4 way interleaved decoder - Google Patents

2/4 way interleaved decoder

Info

Publication number
KR910008571A
KR910008571A KR1019890015832A KR890015832A KR910008571A KR 910008571 A KR910008571 A KR 910008571A KR 1019890015832 A KR1019890015832 A KR 1019890015832A KR 890015832 A KR890015832 A KR 890015832A KR 910008571 A KR910008571 A KR 910008571A
Authority
KR
South Korea
Prior art keywords
input
input signal
nand gate
nand
nand gates
Prior art date
Application number
KR1019890015832A
Other languages
Korean (ko)
Other versions
KR970005643B1 (en
Inventor
정택윤
Original Assignee
이헌조
주식회사 금성사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 이헌조, 주식회사 금성사 filed Critical 이헌조
Priority to KR1019890015832A priority Critical patent/KR970005643B1/en
Publication of KR910008571A publication Critical patent/KR910008571A/en
Application granted granted Critical
Publication of KR970005643B1 publication Critical patent/KR970005643B1/en

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory

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  • Dram (AREA)

Abstract

내용 없음.No content.

Description

2/4웨이(way)인터리브 디코더2/4 way interleave decoder

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 종래의 피롬주변회로를 나타낸 구성도.1 is a block diagram showing a conventional pyromium peripheral circuit.

제2도는 본 발명의 피롬(PROM)주변회로를 나타낸 구성도.2 is a block diagram showing a PROM peripheral circuit of the present invention.

제3도는 제1도의 피롬내부 TTL구성도.3 is an internal PTL configuration of FIG.

제4도는 본 발명에 따른 인터리브 타이밍도.4 is an interleaved timing diagram in accordance with the present invention.

제5도의 (a)(b)는 인터리브 메모리구조도.(A) and (b) of FIG. 5 are interleaved memory structure diagrams.

제6도는 제5도의 설명을 위한 도표도.FIG. 6 is a diagram for explanation of FIG. 5. FIG.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

I1,I2 : 인버터게이트부 MNA1-MNA3 : 낸드게이트부I1, I2: Inverter gate section MNA1-MNA3: NAND gate section

GI-G4 : 버퍼 RSAø-RSA3 : 출력신호GI-G4: Buffer RSAø-RSA3: Output Signal

A19-A23 : 어드레스신호 Ref : 리프레쉬신호A19-A23: address signal Ref: refresh signal

Claims (1)

중앙처리장치의 하이(H) 어드레스로 디코딩하는 인터리브디코더에 있어서, 출력신호(RAS), (CAS)를 디코더하는 입력신호(A19-A23)를 인버터케이트부(I1)를 통해 낸드게이트(NA1)의 입력에 연결하고, 인터리브 모드를 선택하는 입력신호(Sø-S1)는 낸드게이트부(MAN1-MAN3)의 입력에 연결함과 아울러 인터버부(I2)를 통해 낸드게이트부(MAN1-MAN3)의 다른 입력에 연결하고, 현재의 주기가 메모리인지를 구별하는 입력신호(MIO)는 낸드게이트부(MNA1-MNA3)의 다른 입력에 연결하며, 액티브로우로 디램이 리프레쉬 사이클이라는 것을 나타내는 입력신호(Ref)는 낸드게이트(NA2-NA5)의 입력에 연결하고, 상기 낸드게이트(NA1)와 낸드게이트(MNA1-MNA3)의 출력은 각 낸드게이트(NA2-NA5)와 버퍼(G1-G4)에 연결하여 출력신호(BASø-RAS3), (CASø-CAS3)의 디코딩을 중앙처리장치의 로우어드레스(A1, A2)로 디코딩하게 하는 것을 특징으로 한 2/4웨이(way)인터리브 디코더.In an interleave decoder that decodes to a high (H) address of a central processing unit, the NAND gate NA1 receives an input signal A19-A23 that decodes the output signals RAS and CAS through the inverter gate unit I1. The input signal Sø-S1, which is connected to the input of the signal and selects the interleaved mode, is connected to the input of the NAND gate parts MAN1-MAN3, and is connected to the input of the NAND gate parts MAN1-MAN3 through the interleaver part I2. The input signal MIO connected to the other input and distinguishing whether the current period is a memory is connected to the other input of the NAND gate units MNA1-MNA3, and the input signal Ref indicating that the DRAM is in the refresh cycle is active low. ) Is connected to the inputs of the NAND gates (NA2-NA5), and the outputs of the NAND gates (NA1) and NAND gates (MNA1-MNA3) are connected to the respective NAND gates (NA2-NA5) and buffers (G1-G4). Decoding of output signals (BASø-RAS3) and (CASø-CAS3) to the low address (A1, A2) of the central processing unit A 2/4 way (way) interleaving the decoder is characterized in that the decoding. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019890015832A 1989-10-31 1989-10-31 2/4 way interleave decoder KR970005643B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019890015832A KR970005643B1 (en) 1989-10-31 1989-10-31 2/4 way interleave decoder

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019890015832A KR970005643B1 (en) 1989-10-31 1989-10-31 2/4 way interleave decoder

Publications (2)

Publication Number Publication Date
KR910008571A true KR910008571A (en) 1991-05-31
KR970005643B1 KR970005643B1 (en) 1997-04-18

Family

ID=19291270

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019890015832A KR970005643B1 (en) 1989-10-31 1989-10-31 2/4 way interleave decoder

Country Status (1)

Country Link
KR (1) KR970005643B1 (en)

Also Published As

Publication number Publication date
KR970005643B1 (en) 1997-04-18

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