KR910003826A - 저 전류 레벨에서 개선된 성능을 갖는 저 잡음 및 고 이득의 mesfet 제조방법 - Google Patents

저 전류 레벨에서 개선된 성능을 갖는 저 잡음 및 고 이득의 mesfet 제조방법 Download PDF

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Publication number
KR910003826A
KR910003826A KR1019900009621A KR900009621A KR910003826A KR 910003826 A KR910003826 A KR 910003826A KR 1019900009621 A KR1019900009621 A KR 1019900009621A KR 900009621 A KR900009621 A KR 900009621A KR 910003826 A KR910003826 A KR 910003826A
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South Korea
Prior art keywords
mesfet
low noise
high gain
improved performance
substrate
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KR1019900009621A
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English (en)
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케이.내어 비제이
우 슈차이-이
멜렌 닐
Original Assignee
빈센트 죠셉 로너
모토로라 인코포레이티드
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Publication of KR910003826A publication Critical patent/KR910003826A/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/2654—Bombardment with radiation with high-energy radiation producing ion implantation in AIIIBV compounds
    • H01L21/26546—Bombardment with radiation with high-energy radiation producing ion implantation in AIIIBV compounds of electrically active species
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/2654—Bombardment with radiation with high-energy radiation producing ion implantation in AIIIBV compounds
    • H01L21/26546—Bombardment with radiation with high-energy radiation producing ion implantation in AIIIBV compounds of electrically active species
    • H01L21/26553—Through-implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Toxicology (AREA)
  • Health & Medical Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

내용 없음.

Description

저 전류 레벨에서 개선된 성능을 갖는 저 잡음 및 고 이득의 MESFET 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도 및 제2도는 서로 다른 제조 단계에서의 MESFET포션에 대한 확대 단면도,
제3도는 MESFET채널 영역을 형성하는데 이용되는 두개의 이온 주입 조건에 있어서의 기판 저항 대 잡음 지수에 대한 그래프도,
제4도는 MESFET채널 형역을 형성하는데 이용되는 두개의 이온 주입 조건에 있어서의 기파 저항 대 관련 이득에 대한 그래프도.

Claims (3)

  1. 저 전류 레벨에서 개선된 성능을 갖는 저 잡음 및 이득의 MESFET제조 방법에 있어서, 고 저항성의 반절연 갈륨 비소화물 기판을 제공하고, 샤프한 도펀트 프로필을 갖는 채널 영역을 형성시키기 위해서, 소정의 이온 주입 에너지로 N형 도펀프의 소정 도오즈를 기판내에 이온 주입시키는 단계로 이루어진 저 잡음 및 고 이득의 MESFET제조 방법.
  2. 저 전류 레벨에서 개선된 성능을 갖는 저 잡음 및 고 이득의 MESFET제조 방법에 있어서, 대략 5×107ohm-㎝보다 큰 고 저항성의 반절연 갈륨 비소화물 기판을 제공하고, 샤프한 도펀트 프로필을 갖는 채널 영역을 형성하기 위해서 대략 110 내지 140keV의 이온 주입 에너지로 대략 6×1012atoms/㎠도오즈의 실리콘 도펀트를 기판내에 이온 주입시키는 단계로 이루어진 저 잡음 및 고 이득의 MESFET제조 방법.
  3. 저 전류 레벨에서 개선된 성능을 갖는 저 잡음 및 고 이득의 MESFET제조 방법에 있어서, 고 저항성의 반절연 갈륨 비소화물 기판을 제공하고, 샤프한 도펀트 프로필을 갖는 채널 영역을 형성시키기 위해서, 소정의 이온 주입 에너지로 소정 도오즈의 N형 도펀트를 기판내에 이온 주입시키고 그리고 도펀트 프로필을 증진시키기 위해서 P형 도펀트를 기판내에 이온 주입시키는 단계로 이루어진 저 잡음 및 고 이득의 MESFET제조 방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019900009621A 1989-07-03 1990-06-28 저 전류 레벨에서 개선된 성능을 갖는 저 잡음 및 고 이득의 mesfet 제조방법 KR910003826A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US37517689A 1989-07-03 1989-07-03
US375176 1989-07-03

Publications (1)

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KR910003826A true KR910003826A (ko) 1991-02-28

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KR1019900009621A KR910003826A (ko) 1989-07-03 1990-06-28 저 전류 레벨에서 개선된 성능을 갖는 저 잡음 및 고 이득의 mesfet 제조방법

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EP (1) EP0407130A1 (ko)
JP (1) JPH0346224A (ko)
KR (1) KR910003826A (ko)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5766695A (en) * 1996-11-27 1998-06-16 Hughes Electronics Corporation Method for reducing surface layer defects in semiconductor materials having a volatile species
KR100520628B1 (ko) 2003-12-26 2005-10-13 주식회사 하이닉스반도체 반도체 소자의 제조 방법
JP2012022021A (ja) 2010-07-12 2012-02-02 Sony Corp 符号化装置および符号化方法、復号装置および復号方法、並びにプログラム
DE102013101323B4 (de) 2013-02-11 2015-12-24 Epcos Ag Filterbauelement

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3005733A1 (de) * 1980-02-15 1981-08-20 Siemens AG, 1000 Berlin und 8000 München Verfahren zur herstellung einer halbleiteranordnung und nach diesem verfahren hergestellte halbleiteranordnung
US4391651A (en) * 1981-10-15 1983-07-05 The United States Of America As Represented By The Secretary Of The Navy Method of forming a hyperabrupt interface in a GaAs substrate
DE3381683D1 (de) * 1982-11-29 1990-07-26 Fujitsu Ltd Feldeffekttransistor und verfahren zu seiner herstellung.

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EP0407130A1 (en) 1991-01-09
JPH0346224A (ja) 1991-02-27

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