KR910002141A - 노이즈 세이핑형 재 양자화 회로 - Google Patents

노이즈 세이핑형 재 양자화 회로 Download PDF

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Publication number
KR910002141A
KR910002141A KR1019900007693A KR900007693A KR910002141A KR 910002141 A KR910002141 A KR 910002141A KR 1019900007693 A KR1019900007693 A KR 1019900007693A KR 900007693 A KR900007693 A KR 900007693A KR 910002141 A KR910002141 A KR 910002141A
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KR
South Korea
Prior art keywords
requantization
digital signal
represented
signal
output signal
Prior art date
Application number
KR1019900007693A
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English (en)
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KR940003197B1 (ko
Inventor
가즈야 도요마끼
Original Assignee
다까노 시즈오
니뽕 빅터 가부시끼가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 다까노 시즈오, 니뽕 빅터 가부시끼가이샤 filed Critical 다까노 시즈오
Publication of KR910002141A publication Critical patent/KR910002141A/ko
Application granted granted Critical
Publication of KR940003197B1 publication Critical patent/KR940003197B1/ko

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66—Digital/analogue converters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
    • H03M7/30—Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
    • H03M7/3002—Conversion to or from differential modulation
    • H03M7/3004—Digital delta-sigma modulation
    • H03M7/3015—Structural details of digital delta-sigma modulators
    • H03M7/3031—Structural details of digital delta-sigma modulators characterised by the order of the loop filter, e.g. having a first order loop filter in the feedforward path
    • H03M7/3042—Structural details of digital delta-sigma modulators characterised by the order of the loop filter, e.g. having a first order loop filter in the feedforward path the modulator being of the error feedback type, i.e. having loop filter stages in the feedback path only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
    • H03M7/30—Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
    • H03M7/3002—Conversion to or from differential modulation
    • H03M7/3004—Digital delta-sigma modulation
    • H03M7/3015—Structural details of digital delta-sigma modulators
    • H03M7/302—Structural details of digital delta-sigma modulators characterised by the number of quantisers and their type and resolution
    • H03M7/3024—Structural details of digital delta-sigma modulators characterised by the number of quantisers and their type and resolution having one quantiser only
    • H03M7/3028—Structural details of digital delta-sigma modulators characterised by the number of quantisers and their type and resolution having one quantiser only the quantiser being a single bit one

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Analogue/Digital Conversion (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)

Abstract

내용 없음

Description

노이즈 세이핑형 재 양자화 회로
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 노이즈 세이핑형 재 양자화 회로의 개략 구성을 나타내는 블럭도,
제2도는 안정성의 설명을 위한 도면,
제3도 내지 제8도는 본 발명의 노이즈 세이핑형 재 양자화 회로중에 사용되는 대표적인 연산 회로의 구성예를 나타내는 블럭도.

Claims (1)

  1. 높은 분해능을 가지고 있는 입력 디지털 신호의 원표본화 주파수에 비하여 충분하게 높은 재표분화 주파수로서 상기 입력 디지털 신호를 저분해능의 재 양자화 출력 신호로 변환되는 노이즈 세이핑형 재 양자화 회로에 있어서, Z영역에서 상기 입력 디지털 진호를 X(Z), 상기 재 양자화 출력 신호를 Y(Z)로 나타내고, Z-1이 재표본화 주기에 상당하는 단위 지연을 나타내는 것으로서, 상기의 입력 디지털 신호 X(Z)와 상기의 재 양자화 출력 신호 Y(Z)가 공급되어, 각 정수 b, c, d, e가 다음의 각 관계식
    b≥1/2, e≥0, d+e＞0
    b(d+e) (e+d+e)-b2e-1.2(d+e)2＞0
    8b+4c+2d+e＜15
    8b+4c+2d＜14+e
    를 동시에 만족하는 임의의 정수로 하는 다음식
    X(Z)+Z-1 ·{X(Z)-Y(Z)}
    로서 나타내는 신호를 생성하는 연산회로와, 상기의 연산회로에서의 출력 신호가 공급되어, 분해능이 저감된 상기 재 양자화 출력 신호를 출력하는 재 양자화기를 갖추게 되는 노이즈 세이핑형 재 양자화 회로.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019900007693A 1989-06-05 1990-05-28 노이즈 세이핑형 재 양자화 회로 KR940003197B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP142,346 1989-06-05
JP1142346A JPH07109991B2 (ja) 1989-06-05 1989-06-05 ノイズシェーピング型再量子化回路
JP1-142346 1989-06-05

Publications (2)

Publication Number Publication Date
KR910002141A true KR910002141A (ko) 1991-01-31
KR940003197B1 KR940003197B1 (ko) 1994-04-15

Family

ID=15313229

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019900007693A KR940003197B1 (ko) 1989-06-05 1990-05-28 노이즈 세이핑형 재 양자화 회로

Country Status (5)

Country Link
US (1) US5027119A (ko)
EP (1) EP0402742B1 (ko)
JP (1) JPH07109991B2 (ko)
KR (1) KR940003197B1 (ko)
DE (1) DE69026865T2 (ko)

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US5124703A (en) * 1990-04-05 1992-06-23 Matsushita Electric Industrial Co., Ltd. Digital signal requantizing circuit using multistage noise shaping
US5736950A (en) * 1995-01-31 1998-04-07 The United States Of America As Represented By The Secretary Of The Navy Sigma-delta modulator with tunable signal passband
DE19509117C2 (de) * 1995-03-17 1997-02-27 Bosch Gmbh Robert Verfahren zur Überwachung der Übertragungsqualität digitalisierter Signale
AU721526B2 (en) * 1996-03-28 2000-07-06 Toccata Technology Aps Conversion of a PCM signal into a UPWM signal
US6373417B1 (en) * 1999-02-23 2002-04-16 Cirrus Logic, Inc. Digital to analog converter using level and timing control signals to cancel noise
US6816100B1 (en) * 1999-03-12 2004-11-09 The Regents Of The University Of California Analog-to-digital converters with common-mode rejection dynamic element matching, including as used in delta-sigma modulators
US6404369B1 (en) * 2000-09-29 2002-06-11 Teradyne, Inc. Digital to analog converter employing sigma-delta loop and feedback DAC model
DE10051153B4 (de) * 2000-10-16 2004-08-26 Accuride International Gmbh Gargutträgersystem für einen Backofen
DE102005041917A1 (de) * 2005-09-03 2007-03-08 Schaeffler Kg Tandemschrägkugellager
US9209791B2 (en) * 2013-09-06 2015-12-08 Texas Instruments Incorporated Circuits and methods for cancelling nonlinear distortions in pulse width modulated sequences

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FR2462062A1 (fr) * 1979-07-20 1981-02-06 Petit Jean P Codeur delta sigma a double integration analogique et codeur delta sigma a double integration numerique
DE3021012C2 (de) * 1980-06-03 1985-08-22 ANT Nachrichtentechnik GmbH, 7150 Backnang Verallgemeinertes interpolativers Verfahren zur Digital-Analog-Umsetzung von PCM Signalen
US4467291A (en) * 1981-11-23 1984-08-21 U.S. Philips Corporation Delta modulator having optimized loop filter
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DE3232558A1 (de) * 1982-09-01 1984-03-01 Siemens AG, 1000 Berlin und 8000 München Digitaler dpcm-kodierer mit hoher verarbeitungsgeschwindigkeit
DE3232516A1 (de) * 1982-09-01 1984-03-01 Siemens AG, 1000 Berlin und 8000 München Schneller dpcm-kodierer
CA1220867A (en) * 1983-07-18 1987-04-21 Northern Telecom Limited Adaptive differential pcm system with residual-driven adaptation of feedback predictor
EP0173983B1 (en) * 1984-08-30 1992-12-30 Fujitsu Limited Differential coding circuit
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Also Published As

Publication number Publication date
DE69026865D1 (de) 1996-06-13
JPH037415A (ja) 1991-01-14
DE69026865T2 (de) 1996-12-05
US5027119A (en) 1991-06-25
EP0402742A2 (en) 1990-12-19
KR940003197B1 (ko) 1994-04-15
EP0402742A3 (en) 1992-09-02
JPH07109991B2 (ja) 1995-11-22
EP0402742B1 (en) 1996-05-08

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