KR900013630A - Method for manufacturing flat capacitor connected to NOSFET and apparatus therefor - Google Patents

Method for manufacturing flat capacitor connected to NOSFET and apparatus therefor Download PDF

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Publication number
KR900013630A
KR900013630A KR1019890002377A KR890002377A KR900013630A KR 900013630 A KR900013630 A KR 900013630A KR 1019890002377 A KR1019890002377 A KR 1019890002377A KR 890002377 A KR890002377 A KR 890002377A KR 900013630 A KR900013630 A KR 900013630A
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South Korea
Prior art keywords
electrode
insulator
region
capacitor
gate
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KR1019890002377A
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Korean (ko)
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KR910008119B1 (en
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김재갑
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정몽헌
현대전자산업 주식회사
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Publication of KR900013630A publication Critical patent/KR900013630A/en
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Publication of KR910008119B1 publication Critical patent/KR910008119B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

내용 없음No content

Description

MOSFET에 접속된 평탄캐퍼시터 제조방법 및 그 장치Method for manufacturing flat capacitor connected to MOSFET and apparatus therefor

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제4도는 본 발명에 따라 형성된 마스크배열 평면도.4 is a plan view of a mask array formed in accordance with the present invention.

제5도 제4도의 a-a'축을 절단하여 제조공정을 나타내는 단면도.Sectional drawing which shows the manufacturing process by cutting the a-a 'axis | shaft of FIG.

Claims (5)

P형 실리콘 기판상부에 평판캐퍼시터를 형성하고 MOSFET를 형성하여 평판캐퍼시터의 전하보족 전극이 드레인 전극에 접속된 반도체 기억장치의 제조방법에 있어서, P형 실리콘에 게이트 산화막, 게이트 전도 물질 및 절연체를 순차적으로, 형성하고 게이트 마스크를 이용하여 개이트 전극 부분만 남기고 상기 절연체, 게이트 전도물질 및 게이트 산화막을 제거하는 단계와, 게이트 전극측면 하단에 드레인 N형영역 및 소오스 N형영역을 형성하고 게이트 전극 상부에 절연체를 그대로 남기고 측벽에는 절연체 스페이서를 형성하는 단계와, 전하보존 전극 마스크를 사용하여 감광물질을 게이트 전극 일정 상부에 형성하고 실리콘 기판상부에 P-형 불순물을 깊게 이온주입한 후, P-형 불순물 상부에 N형 불순물을 얇게 이온주입하여 전하보존전극영역을 형성하는 단계와, 상기 전하보존전극 영역상부에 캐패시터 유전체를 형성하고 플레이트 전극용 전도물질을 전영역상부에 침착한 후 플레이트 전극 마스크를 사용하여 일정부분 제거하고 플레이트 전극을 형성하는 단계로 이루어지는 것을 특징으로 하는 MOSFET에 접속된 평판캐패시터 제조방법.A method of manufacturing a semiconductor memory device in which a plate capacitor is formed on a P-type silicon substrate, and a MOSFET is formed so that the charge-holding electrode of the plate capacitor is connected to the drain electrode. A gate oxide film, a gate conducting material, and an insulator are sequentially formed on the P-type silicon. Removing the insulator, the gate conductive material, and the gate oxide layer using only a gate electrode, and forming a drain N-type region and a source N-type region at the bottom of the gate electrode side by after deeply ion-implanted type impurity, P - - to leave the insulator as the side wall is formed in the step of forming an insulating spacer, and a photosensitive material using a charge conservation electrode mask, to a gate electrode constant upper and P in the upper silicon substrate type Form a charge storage electrode region by thinly implanting N-type impurities on top of impurities And forming a capacitor dielectric on the charge storage electrode region, depositing a conductive material for the plate electrode on the entire region, and then removing a portion using a plate electrode mask to form a plate electrode. A flat capacitor manufacturing method connected to a MOSFET. 제1항에 있어서, 상기 전하보존전극 영역을 형성하는 단계에서, 소자분리 산화막 드리엔 M형영역, 게이트 전극 및 소오스 N형영역의 전영역상에 도포된 감광물질을 전하보존전극 마스크를 사용하여 게이트 전극상부 일정부분 및 소오스 N형영역 상부에 남기고 제거하는 것을 특징으로 하는 MOSFET에 접속된 평판캐패시터 제조방법.The method of claim 1, wherein in the forming of the charge storage electrode region, the photosensitive material applied to the entire region of the device isolation oxide driene M-type region, the gate electrode, and the source N-type region is formed using a charge storage electrode mask. A method of manufacturing a flat capacitor connected to a MOSFET, which comprises removing a portion of the gate electrode and an upper portion of the source N-type region. 실리콘 기판 상부에 평판캐퍼시터는 MOSFET의 드레인 전극에 접속된 반도체 기억장치에 있어서, 상부에 절연체가 형성된 MOSFET의 게이트 전극 측면에는 절연체 스페이서가 형성되고 드레인 N형영역에 평판캐퍼시터 유전체가 형성되고 그 상부에 플레이트 전극용 전도물질이 게이트 전극의 절연체 상부 일정부분까지 형성된 구조를 특징으로 하는 MOSFET에 접속된 평판캐퍼시터 장치.In a semiconductor memory device in which a flat plate capacitor is connected to a drain electrode of a MOSFET on top of a silicon substrate, an insulator spacer is formed on a side of a gate electrode of a MOSFET having an insulator formed thereon, and a flat plate capacitor dielectric is formed on the drain N-type region. A flat capacitor device connected to a MOSFET characterized by a structure in which a conductive material for a plate electrode is formed up to a predetermined portion of an insulator on a gate electrode. 제3항에 있어서, 상기 전하보존전극은 게이트 전극상부 및 절연체 스페이서를 장벽층으로 하여 자기정렬된 구조로 이루어지는 것을 특징으로 하는 MOSFET에 접속된 평판캐패시터 장치.4. The flat panel capacitor device of claim 3, wherein the charge storage electrode has a self-aligned structure using a gate electrode upper portion and an insulator spacer as a barrier layer. 제3또는 4항에 있어서, 상기 절연체 스페이서는 질화막 또는 산화막인 것을 특징으로 하는 MOSFET에 접속된 평판캐패시터 장치.The flat panel capacitor device of claim 3 or 4, wherein the insulator spacer is a nitride film or an oxide film. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019890002377A 1989-02-28 1989-02-28 Planner capacitor device and method of fabricating thereof KR910008119B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019890002377A KR910008119B1 (en) 1989-02-28 1989-02-28 Planner capacitor device and method of fabricating thereof

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Application Number Priority Date Filing Date Title
KR1019890002377A KR910008119B1 (en) 1989-02-28 1989-02-28 Planner capacitor device and method of fabricating thereof

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KR900013630A true KR900013630A (en) 1990-09-06
KR910008119B1 KR910008119B1 (en) 1991-10-10

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