KR900017186A - Semiconductor Memory and Manufacturing Method - Google Patents

Semiconductor Memory and Manufacturing Method Download PDF

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Publication number
KR900017186A
KR900017186A KR1019890004349A KR890004349A KR900017186A KR 900017186 A KR900017186 A KR 900017186A KR 1019890004349 A KR1019890004349 A KR 1019890004349A KR 890004349 A KR890004349 A KR 890004349A KR 900017186 A KR900017186 A KR 900017186A
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KR
South Korea
Prior art keywords
forming
impurities
gate electrode
trench
electrode
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KR1019890004349A
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Korean (ko)
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KR910008121B1 (en
Inventor
김재갑
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정몽헌
현대전자산업 주식회사
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Priority to KR1019890004349A priority Critical patent/KR910008121B1/en
Publication of KR900017186A publication Critical patent/KR900017186A/en
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Publication of KR910008121B1 publication Critical patent/KR910008121B1/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
    • H10B12/0385—Making a connection between the transistor and the capacitor, e.g. buried strap
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)

Abstract

내용 없음.No content.

Description

반도체 기억장치 및 그 제조방법Semiconductor Memory and Manufacturing Method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

Claims (5)

실리콘 기판상에 MOSFET와 트렌치 캐패시터로 이루어진 반도체 기억장치 제조방법에 있어서, 실리콘 기판(1) 상부에 게이트 전극을 형성하고 소오스 및 드레인영역(6 및 6')에 저농도의 불순물을 도핑시켜 소오스 및 드레인 영역을 형성한 다음, 게이트 전극 측벽에 절연체 스페이서(8)를 형성하여 MOSFET를 먼저 형성하는 단계와, 상기 드레인영역(6') 측면의 실리콘 기판(1)내로 트렌치를 식각하고 트렌치 측벽에 불순물 확산영역(14) 및 전하보존전극(16)을 각각 형성하는 단계와, 상기 전할보존전극 상부에 캐패시터 유전체막(17)을 형성하고 그 상부에 셀플레이트 전극을 형성하는 단계로 이루어진 것을 특징으로 하는 반도체 기억장치 제조방법.In the method of manufacturing a semiconductor memory device comprising a MOSFET and a trench capacitor on a silicon substrate, a gate electrode is formed on the silicon substrate 1, and a low concentration of impurities are doped in the source and drain regions 6 and 6 'so that the source and drain are formed. Forming a region, and then forming an insulator spacer 8 on the gate electrode sidewalls to form a MOSFET first, etching the trench into the silicon substrate 1 on the side of the drain region 6 'and diffusing impurities in the trench sidewalls. Forming a region 14 and a charge storage electrode 16, and forming a capacitor dielectric film 17 over the charge storage electrode and forming a cell plate electrode thereon. Memory manufacturing method. 제1항에 있어서, 상기 트렌치 벽면의 전하보존전극(16)을 형성하는 단계는, 마스크를 사용치 않고 상기 불순물을 확산영역(14)과 반대형의 고농도 불순물이 도프된 산화막(15)을 트렌치, 소오스 및 드레인영역(6 및 6') 및, 게이트 전극 그리고 소자분리 산화막(2) 상부에 침착한 후, 고온의 열처리 공정에 의해 고농도 불순물이 도포된 산화막(15)으로부터 불순물이 얇게 확산되어 형성되는 것을 특징으로 하는 반도체 기억장치 제조방법.The method of claim 1, wherein the forming of the charge storage electrode 16 on the trench wall surface comprises: trenching the oxide film 15 doped with a high concentration of impurities opposite to the diffusion region 14 without using a mask. Is deposited on top of the source and drain regions 6 and 6 ', the gate electrode and the device isolation oxide film 2, and is then formed by thinly diffusing impurities from the oxide film 15 coated with high concentration impurities by a high temperature heat treatment process. Method for manufacturing a semiconductor memory device, characterized in that. 제1 또는 2항에 있어서, 상기 전하보존전극(16)을 형성하는 단계에서, 상기 열처리 공정에 의해 고농도 불순물이 도프된 산화막(15)으로부터 불순물이 상기 트렌치 벽면을 포함하여 소오스 및 드레인영역(6 및 6')에도 선택적으로 확산되는 것을 특징으로 하는 반도체 기억장치 제조방법.3. The source and drain region (6) according to claim 1 or 2, wherein in the step of forming the charge storage electrode (16), impurities from the oxide film (15) doped with a high concentration of impurities by the heat treatment process include the trench wall surface. And 6 '). 제1항에 있어서, 상기 셀플레이트 전극을 형성하는 단계는 셀플레이트 전극용 전도물질(18)을 상기 노출된 전영역 상부에 침착하고 마스크 패턴 공정에 의해 게이트 전극 일정상부까지 셀플레이트전극(18)을 형성하는 것을 특징으로 하는 반도체 기억장치 제조방법.The method of claim 1, wherein the forming of the cell plate electrode comprises depositing a conductive material 18 for the cell plate electrode on the exposed entire area and forming the cell plate electrode 18 up to the gate electrode by a mask pattern process. And forming a semiconductor memory device. 실리콘 기판(1)상에 MOSFET와 트렌치 캐패시터로 접속되어 이루어진 반도체 기억장치에 있어서, 트렌치 캐패시터와 MOSFET간의 거리를 단축시키기 위하여, 트렌치 전영역에 걸쳐 형성된 셀플레이트 전극을 게이트 전극 상부 일정부분까지 겹치도록 형성시키되, 상기 게이트 전극용 전도물질(4) 양측면에는 절연체 스페이서(8)를, 상부에는 절연체(5)를 각각 형성시켜 상기 셀플레이트전극(18)과 게이트전극용 전도물질(4)이 절연된 구조로 이루어진 것을 특징으로 하는 반도체 기억장치.In a semiconductor memory device formed by connecting a MOSFET and a trench capacitor on a silicon substrate 1, in order to shorten the distance between the trench capacitor and the MOSFET, the cell plate electrodes formed over the entire trench are overlapped to a predetermined portion of the gate electrode. The cell plate electrode 18 and the gate electrode conductive material 4 are insulated from each other by forming an insulator spacer 8 on both sides of the gate electrode conductive material 4 and an insulator 5 on the upper side thereof. A semiconductor memory device comprising a structure. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019890004349A 1989-04-03 1989-04-03 Semiconductor memory device and method of fabricating thereof KR910008121B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019890004349A KR910008121B1 (en) 1989-04-03 1989-04-03 Semiconductor memory device and method of fabricating thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019890004349A KR910008121B1 (en) 1989-04-03 1989-04-03 Semiconductor memory device and method of fabricating thereof

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KR900017186A true KR900017186A (en) 1990-11-15
KR910008121B1 KR910008121B1 (en) 1991-10-10

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