KR970018685A - Semiconductor device with gold structure and manufacturing method thereof - Google Patents

Semiconductor device with gold structure and manufacturing method thereof Download PDF

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KR970018685A
KR970018685A KR1019950033418A KR19950033418A KR970018685A KR 970018685 A KR970018685 A KR 970018685A KR 1019950033418 A KR1019950033418 A KR 1019950033418A KR 19950033418 A KR19950033418 A KR 19950033418A KR 970018685 A KR970018685 A KR 970018685A
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oxide film
film
polysilicon
region
sidewall
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KR0170515B1 (en
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윤광준
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김광호
삼성전자 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
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  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

본 발명은 GOLD구조를 갖는 반도체장치 및 그의 제조방법에 관한 것으로서, 그 구성은 활성영역과 필드영역이 정의되어 있고 그리고 상기 활성영역에 LDD 영역(43a)과 고농도의 확산영역(43b)으로 형성된 소오스/드레인 영역이 형성되어 있는 반도체기판(30)과; 상기 반도체기판(30)상에 필드영역에 형성된 소자격리용 산화막(32)과; 상기 활성영역상에 형성된 게이트 산화막(34)과; 상기 게이트산화막(34)상에 형성되어 있고 그리고 사이에 소정두께를 갖는 산화막(38)이 끼워져 있는 제1 및 제2 폴리실리콘막(36, 40)과;상기 제1폴리실리콘막(36)상에서 상기 제2폴리실리콘막(40)과 상기 산화막(38)의 측벽에 형성되고 그리고 상기 제1 및 제2폴리실리콘막(36, 40)을 전기적으로 접속하는 측벽폴리실리콘막(44)과; 상기 게이트산화막(34)상에서 상기 측벽폴리실리콘막(44)과 상기 제1폴리실리콘막(36)의 측벽에 형성된 측벽산화막(46)과; 상기 소오스/드레인영역과 상기 제2폴리실리콘막의 표면에 형성된 콘택부(48)를 포함한다. 상기 GOLD구조에 의해, 측벽폴리실리콘막(46)의 폭에 의해서 게이트와 드레인의 중첩길이가 결정되기 때문에, 그 게이트-드레인 중첩길이의 조절이 용이하고, 그리고 게이트전극으로 사용되는 상기 상하부의 폴리실리콘막(36)(40)의 사이에 소정두께를 갖는 산화막(38)이 형성되어 있기 때문에, 양호한 수직구조를 갖는 폴리실리콘막(40)이 비등방성식각에 의해 용이하게 형성될 수 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a GOLD structure and a method of manufacturing the same, the configuration of which is defined as an active region and a field region, and a source formed of an LDD region 43a and a high concentration diffusion region 43b in the active region. A semiconductor substrate 30 having a / drain region formed thereon; An element isolation oxide film 32 formed in the field region on the semiconductor substrate 30; A gate oxide film 34 formed on the active region; First and second polysilicon films 36 and 40 formed on the gate oxide film 34 and sandwiching an oxide film 38 having a predetermined thickness therebetween; and on the first polysilicon film 36; Sidewall polysilicon films (44) formed on sidewalls of said second polysilicon film (40) and said oxide film (38) and electrically connecting said first and second polysilicon films (36, 40); Sidewall oxide films 46 formed on sidewalls of the sidewall polysilicon film 44 and the first polysilicon film 36 on the gate oxide film 34; And a contact portion 48 formed on the surface of the source / drain region and the second polysilicon layer. Since the overlap length of the gate and drain is determined by the width of the sidewall polysilicon film 46 by the GOLD structure, the gate-drain overlap length can be easily adjusted, and the upper and lower polys used as the gate electrode Since the oxide film 38 having a predetermined thickness is formed between the silicon films 36 and 40, the polysilicon film 40 having a good vertical structure can be easily formed by anisotropic etching.

Description

GOLD구조를 갖는 반도체장치 및 그의 제조방법Semiconductor device with gold structure and manufacturing method thereof

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도는 본 발명의 반도체장치의 구조를 보인 단면도.3 is a cross-sectional view showing the structure of a semiconductor device of the present invention.

Claims (9)

GOLD(gate-drain overlapped LDD) 구조를 갖는 반도체장치에 있어서, 활성영역과 필드영역이 정의되어 있고 그리고 상기 활성영역에 LDD(lightly doped drain) 영역(43a)과 고농도의 확산영역(43b)으로 형성된 소오스/드레인영역이 형성되어 있는 반도체기판(30)과; 상기 반도체기판(30)상에 필드영역에 형성된 소자격리용 산화막(32)과; 상기 활성영역상에 형성된 게이트산화막(34)과; 상기 게이트산화막(36)상에 형성되어 있고 그리고 사이에 소정두께를 갖는 산화막(38)이 끼워져 있는 제1및 제2폴리실리콘막(36, 40)과; 상기 제1폴리실리콘막(36)상에서 상기 제2폴리실리콘막(40)과 상기 산화막(38)의 측벽에 형성되고 그리고 상기 제1및 제2폴리실리콘막(36, 40)을 전기적으로 접속하는 측벽폴리실리콘막(44)과; 상기 게이트산화막(34)상에서 상기 측벽폴리실리콘막(44)과 상기 제1폴리실리콘막(36)의 측벽에 형성된 측벽산화막(46)과; 상기 소오스/드레인영역과 상기 제2폴리실리콘막의 표면에 형성된 콘택부(48)를 포함하는 것을 특징으로 하는 반도체장치의 제조방법.In a semiconductor device having a gate-drain overlapped LDD (GOLD) structure, an active region and a field region are defined, and the active region is formed of a lightly doped drain (LDD) region 43a and a high concentration diffusion region 43b. A semiconductor substrate 30 having a source / drain region formed thereon; An element isolation oxide film 32 formed in the field region on the semiconductor substrate 30; A gate oxide film 34 formed on the active region; First and second polysilicon films 36 and 40 formed on the gate oxide film 36 and sandwiched with an oxide film 38 having a predetermined thickness therebetween; It is formed on the sidewalls of the second polysilicon film 40 and the oxide film 38 on the first polysilicon film 36 and electrically connects the first and second polysilicon films 36 and 40. A sidewall polysilicon film 44; Sidewall oxide films 46 formed on sidewalls of the sidewall polysilicon film 44 and the first polysilicon film 36 on the gate oxide film 34; And a contact portion (48) formed on the surface of said source / drain region and said second polysilicon film. 제1항에 있어서, 상기 콘택부(48)는 실리사이드막인 것을 특징으로 하는 반도체장치.The semiconductor device according to claim 1, wherein said contact portion (48) is a silicide film. GOLD(gate-drain overlapped LDD) 구조를 갖는 반도체장치의 제조방법에 있어서, 반도체기판(30)상에 활성영역(an active region)과 필드영역(a field region)을 정의한 다음, 상기 필드영역에 소자격리용 산화막(32)을 형성하는 공정과; 상기 소자격리용 산화막(32)사이의 활성영역상에 게이트산화막(34)을 형성하는 공정과; 상기 게이트산화막(34)과 상기 소자격리용 산화막(32)상에 도전형의 제1폴리실리콘막(36)과 층간산화막(38)을 차례로 형성하는 공정과; 상기 산화막(38)상에 도전형 제2폴리실리콘막(40)과 상부산화막(42)을 차례로 형성하는 공정과; 소정패턴의 마스크를 사용하여 상기 상부산화막(42)과 상기 제2폴리실리콘막(40) 및 상기 층간산화막(38)을 선택적으로 제거하여 게이트구조물을 형성하는 공정과; 상기 게이트구조물을 마스크로 사용하는 불순물주입을 실행하여 상기 반도체기판(30)에 LDD영역(43a)를 형성하는 공정과; 상기 게이트구조물의 측벽에 도전형의 측벽폴리실리콘막(44)을 형성하는 공정과; 상기 측벽폴리실리콘막(44)이 형성된 상기 게이트구조물을 마스크로 사용하는 불순물주입을 실행하여 고농도의 소오스/드레인 확산영역(43b)을 형성하는 공정과; 상기 측벽폴리실리콘막(44)과 상기 노출된 제1폴리실리콘막(36)의 측벽에 측벽산화막(46)을 형성하는 공정을 포함하는 것을 특징으로 하는 반도체장치의 제조방법.In the method of manufacturing a semiconductor device having a gate-drain overlapped LDD (GOLD) structure, an active region and a field region are defined on the semiconductor substrate 30, and then a small region is formed in the field region. Forming a qualified oxide film 32; Forming a gate oxide film (34) on an active region between the device isolation oxide films (32); Forming a conductive first polysilicon film (36) and an interlayer oxide film (38) sequentially on the gate oxide film (34) and the device isolation oxide film (32); Sequentially forming a conductive second polysilicon film (40) and an upper oxide film (42) on the oxide film (38); Forming a gate structure by selectively removing the upper oxide film (42), the second polysilicon film (40) and the interlayer oxide film (38) using a mask having a predetermined pattern; Forming an LDD region (43a) in the semiconductor substrate (30) by performing impurity implantation using the gate structure as a mask; Forming a conductive sidewall polysilicon film (44) on the sidewalls of the gate structure; Performing impurity implantation using the gate structure on which the sidewall polysilicon film (44) is formed as a mask to form a high concentration source / drain diffusion region (43b); And forming a sidewall oxide film (46) on the sidewalls of said sidewall polysilicon film (44) and said exposed first polysilicon film (36). 제3항에 있어서, 상기 제2폴리실리콘막(40)의 제거공정은 건식시각에 의해 실행되는 것을 특징으로 하는 반도체장치의 제조방법.4. The method of manufacturing a semiconductor device according to claim 3, wherein the step of removing the second polysilicon film (40) is performed by dry vision. 제3항에 있어서, 상기 산화막(38)은 건식 또는 습식식각에 의해 실행되는 것을 특징으로 하는 반도체장치의 제조방법.4. A method according to claim 3, wherein the oxide film (38) is performed by dry or wet etching. 제3항에 있어서, 상기 측벽폴리실리콘막(44)의 형성공정은 폴리실리콘막을 퇴적하는 공정과 이 퇴적된 폴리실리콘막에 불순물이온을 주입하는 공정 및 비등방성 식각을 실행하여 상기 측벽폴리실리콘막(44)을 형성하는 공정을 포함하는 것을 특징으로 하는 반도체장치의 제조방법.The sidewall polysilicon film of claim 3, wherein the forming of the sidewall polysilicon film 44 is performed by depositing a polysilicon film, implanting impurity ions into the deposited polysilicon film, and performing anisotropic etching. And (44) forming a semiconductor device. 제3항에 있어서, 상기 비등방성 식각을 실행하는 공정이 실행되는 과정에 상기 측벽폴리실리콘막(44)이 형성된 게이트구조물이외의 상기 제1폴리실리콘막(36)이 선택적으로 동시에 제거되는 것을 특징으로 하는 반도체장치의 제조방법.The method of claim 3, wherein the first polysilicon layer 36 other than the gate structure on which the sidewall polysilicon layer 44 is formed is selectively removed simultaneously while the anisotropic etching is performed. A semiconductor device manufacturing method. 제3항에 있어서, 상기 측벽산화막(46)의 형성공정을 실행하는 과정에 상기 제2폴리실리콘막(40)상에 있는 상기 산화막(42)과, 상기 구조물과 상기 소자격리용 산화막(32)사이의 게이트산화막(34)이 선택적으로 동시에 제거되는 것을 포함하는 것을 특징으로 하는 반도체장치의 제조방법.4. The oxide film 42, the structure, and the device isolation oxide film 32 on the second polysilicon film 40 in the process of forming the sidewall oxide film 46. And the gate oxide film (34) is selectively removed at the same time. 제3항에 있어서, 상기 측벽산화막의 형성공정후에 소오스/드레인영역과 게이트영역상에 콘택용 실리사이드막(48)을 형성하는 공정을 포함하는 것을 특징으로 하는 반도체장치의 제조방법.4. The method according to claim 3, further comprising forming a contact silicide film (48) on the source / drain regions and the gate region after the step of forming the sidewall oxide film. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950033418A 1995-09-30 1995-09-30 A semiconductor device with a gold structure and a method of fabricating the same KR0170515B1 (en)

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KR1019950033418A KR0170515B1 (en) 1995-09-30 1995-09-30 A semiconductor device with a gold structure and a method of fabricating the same
JP8170063A JPH09116150A (en) 1995-09-30 1996-06-28 Semiconductor device with gold structure and its manufacture

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KR100567047B1 (en) * 1999-06-28 2006-04-04 주식회사 하이닉스반도체 Menufacturing method for mos transistor
JP4429036B2 (en) 2004-02-27 2010-03-10 富士通マイクロエレクトロニクス株式会社 Manufacturing method of semiconductor device
CN104037084B (en) * 2013-03-05 2017-12-29 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof
CN104103505B (en) * 2013-04-10 2017-03-29 中芯国际集成电路制造(上海)有限公司 The forming method of grid
CN104183473B (en) * 2013-05-21 2017-07-14 中芯国际集成电路制造(上海)有限公司 The forming method and semiconductor devices of metal gate transistor

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