KR900002464A - How to connect capacitor and transistor of semiconductor device - Google Patents

How to connect capacitor and transistor of semiconductor device Download PDF

Info

Publication number
KR900002464A
KR900002464A KR1019880008951A KR880008951A KR900002464A KR 900002464 A KR900002464 A KR 900002464A KR 1019880008951 A KR1019880008951 A KR 1019880008951A KR 880008951 A KR880008951 A KR 880008951A KR 900002464 A KR900002464 A KR 900002464A
Authority
KR
South Korea
Prior art keywords
poly
transistor
mask layer
connection
substrate
Prior art date
Application number
KR1019880008951A
Other languages
Korean (ko)
Other versions
KR920003318B1 (en
Inventor
남인호
Original Assignee
강진구
삼성반도체통신 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 강진구, 삼성반도체통신 주식회사 filed Critical 강진구
Priority to KR1019880008951A priority Critical patent/KR920003318B1/en
Publication of KR900002464A publication Critical patent/KR900002464A/en
Application granted granted Critical
Publication of KR920003318B1 publication Critical patent/KR920003318B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Semiconductor Memories (AREA)

Abstract

내용 없음No content

Description

반도체 소자의 커패시터와 트랜지스터의 연결방법How to connect capacitor and transistor of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도 (A)-(C)는 본 발명의 제1실시예에 따른 커패시터와 트랜지스터의 연결방법을 설명하기 위한 각 공정별 수직 단면도.2A to 2C are vertical cross-sectional views of respective processes for explaining a method of connecting a capacitor and a transistor according to the first embodiment of the present invention.

제3도 (A)-(C)는 본 발명의 제2실시예의 각 공정별 수직 단면도.3 (A)-(C) are vertical sectional views of respective processes of the second embodiment of the present invention.

제4도 (A)-(C)는 본 발명의 제3실시예의 각 공정별 수직 단면도.4 (A)-(C) are vertical sectional views of respective processes of the third embodiment of the present invention.

Claims (4)

반도체 메모리 소자의 커패시터 및 트랜지스터 연결방법에 있어서, 트랜치 커패시터가 형성된 기판(1)의 전면을 평탄화한 후 산호막(4)을 기르고 접속창을 내는 공정과, 기판(1)의 전면에 폴리(6)와 마스크층(7)을 침적한 후 상기 마스크층의 패턴을 이용하여 연결 폴리(6a)부분 이외의 폴리와 필드를 산화하는 공정과, 상기 산화 폴리를 제거하는 공정과로 되는 반도체 소자의 커패시터와 트랜지스터의 연결방법.In a method of connecting a capacitor and a transistor of a semiconductor memory device, a process of growing a coral film 4 and opening a connection window after planarizing the entire surface of the substrate 1 on which the trench capacitor is formed, and a poly (6) on the front surface of the substrate 1 ) And the mask layer 7 is deposited, followed by oxidizing the poly and the field other than the connecting poly 6a portion using the pattern of the mask layer, and removing the oxidized poly capacitor. And transistor connection method. 제1항에 있어서, 기판(1)전면에 폴리(6)와 마스크층(7)을 침적하는 공정 이후, 연결폴리(6b)이외의 부분의 마스크층(7)을 제거하는 공정과, 연결폴리(6b)윗부분을 산화시키고 나머지 폴리(6)를 식각하는 공정과로 되는 것을 특징으로 하는 반도체 소자의 커패시터의 연결방법.The process according to claim 1, wherein after the step of depositing the poly 6 and the mask layer 7 on the entire surface of the substrate 1, the step of removing the mask layer 7 in portions other than the connection poly 6b, and the connection poly And (6b) oxidizing the upper portion and etching the remaining poly (6). 제1항에 있어서, 기판(1)전면에 폴리(6)와 마스크층(7)을 침적하는 공정 이후, 연결폴리(6b)가 형성될 부분이외의 부분은 마스크층(7)을 제거하고, 이어서 상기 폴리(6)를 산화제거하는 공정과로 되는 것을 특징으로 하는 반도체 소자의 커패시터와 트랜지스터의 연결방법.The method of claim 1, wherein after the process of depositing the poly 6 and the mask layer 7 on the entire surface of the substrate 1, the portions other than the portion where the connection poly 6b is to be formed are removed from the mask layer 7. And subsequently oxidizing and removing the poly (6). 반도체 소자의 커패시터 및 트랜지스터 연결방법에 있어서, 트랜치 커패시터가 형성된 기판(1)전면을 평탄화한후, 폴리(14)와 산화막(15)을 차례로 형성하는 공정과 연결폴리가 형성될 부분을 마스킹하고 상기 폴리(14)를 산화하는 공정과, 상기 산화폴리(14a)를 제거하여 연결폴리(14b)를 형성하고 난 후 트랜지스터 형성하는 공정과로 되는 것을 특징으로 하는 반도체 소자의 커패시터와 트랜지스터의 연결방법.In the method of connecting a capacitor and a transistor of a semiconductor device, a process of forming a poly 14 and an oxide film 15 in sequence after planarizing the entire surface of the substrate 1 on which the trench capacitor is formed and masking a portion where the connection poly is to be formed is performed. And a step of oxidizing the poly (14), and removing the poly oxide (14a) to form a connecting poly (14b) and then forming a transistor. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019880008951A 1988-07-18 1988-07-18 Connecting method between transistor and capacitor of semiconductor element KR920003318B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019880008951A KR920003318B1 (en) 1988-07-18 1988-07-18 Connecting method between transistor and capacitor of semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019880008951A KR920003318B1 (en) 1988-07-18 1988-07-18 Connecting method between transistor and capacitor of semiconductor element

Publications (2)

Publication Number Publication Date
KR900002464A true KR900002464A (en) 1990-02-28
KR920003318B1 KR920003318B1 (en) 1992-04-27

Family

ID=19276179

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019880008951A KR920003318B1 (en) 1988-07-18 1988-07-18 Connecting method between transistor and capacitor of semiconductor element

Country Status (1)

Country Link
KR (1) KR920003318B1 (en)

Also Published As

Publication number Publication date
KR920003318B1 (en) 1992-04-27

Similar Documents

Publication Publication Date Title
US4478679A (en) Self-aligning process for placing a barrier metal over the source and drain regions of MOS semiconductors
KR940016682A (en) Electrical isolation structure and integrated method in integrated circuit
KR950021084A (en) Simultaneous Formation of Metal Wires and Contact Plugs
KR900002464A (en) How to connect capacitor and transistor of semiconductor device
KR910005458A (en) Manufacturing Method of Semiconductor Equipment
KR890004415A (en) Device Separation Method of Semiconductor Device
KR100189723B1 (en) Semiconductor cell manufacturing method using epi-si deposition
KR950021367A (en) Device Separation Method of Semiconductor Device
KR940016887A (en) Method of forming fine gate electrode of semiconductor device
KR960026210A (en) Fine contact formation method
KR950004583A (en) Thin Film Transistor Manufacturing Method
KR980003884A (en) Resist Pattern Formation Method
KR900002402A (en) Semiconductor manufacturing method with reduced toppertage due to field separation
KR960026867A (en) Manufacturing method of semiconductor device
KR920013625A (en) Ion Implantation Method of Semiconductor Device
KR950004539A (en) Semiconductor Memory and Manufacturing Method
KR950021401A (en) Trench Type Device Separator Manufacturing Method
KR900002419A (en) A method of forming a high concentration source region and a capacitor surface region of a semiconductor device using a selective sidewall doping technique (SSWDT) and the semiconductor integrated device
KR900002420A (en) Method of forming high concentration source region and capacitor surface region of semiconductor device using selective sidewall doping technique (SSWDT)
KR960026127A (en) Recess Array Formation of Highly Integrated Semiconductor Devices
KR910017684A (en) Memory Cell Capacitor Manufacturing Method
KR920013702A (en) Manufacturing method in stepped area for conductive layer connection
KR980011844A (en) Semiconductor device manufacturing method
JPS641065B2 (en)
KR960035807A (en) Contact hole formation method of semiconductor device

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E902 Notification of reason for refusal
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20050310

Year of fee payment: 14

LAPS Lapse due to unpaid annual fee