KR890702144A - 핀수가 적은 고속버스 인터페이스 - Google Patents
핀수가 적은 고속버스 인터페이스Info
- Publication number
- KR890702144A KR890702144A KR1019880701768A KR880701768A KR890702144A KR 890702144 A KR890702144 A KR 890702144A KR 1019880701768 A KR1019880701768 A KR 1019880701768A KR 880701768 A KR880701768 A KR 880701768A KR 890702144 A KR890702144 A KR 890702144A
- Authority
- KR
- South Korea
- Prior art keywords
- bus interface
- speed bus
- pin count
- low pin
- low
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
- G06F13/4072—Drivers or receivers
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US07/044,780 US4774422A (en) | 1987-05-01 | 1987-05-01 | High speed low pin count bus interface |
US044,780 | 1987-05-01 | ||
PCT/US1988/001276 WO1988008581A1 (en) | 1987-05-01 | 1988-04-26 | High speed low pin count bus interface |
Publications (2)
Publication Number | Publication Date |
---|---|
KR890702144A true KR890702144A (ko) | 1989-12-23 |
KR910007649B1 KR910007649B1 (ko) | 1991-09-28 |
Family
ID=21934307
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019880701768A KR910007649B1 (ko) | 1987-05-01 | 1988-04-26 | 핀수가 적은 고속 버스 인터페이스 |
Country Status (8)
Country | Link |
---|---|
US (1) | US4774422A (ko) |
EP (1) | EP0360817B1 (ko) |
JP (1) | JP2532135B2 (ko) |
KR (1) | KR910007649B1 (ko) |
AU (1) | AU599235B2 (ko) |
CA (1) | CA1297197C (ko) |
DE (1) | DE3878908T2 (ko) |
WO (1) | WO1988008581A1 (ko) |
Families Citing this family (29)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4825098A (en) * | 1986-12-17 | 1989-04-25 | Fujitsu Limited | Bidirectional semiconductor device having only one one-directional device |
US4979097A (en) * | 1987-09-04 | 1990-12-18 | Digital Equipment Corporation | Method and apparatus for interconnecting busses in a multibus computer system |
US4835414A (en) * | 1988-03-14 | 1989-05-30 | Advanced Micro Devices, Inc. | Flexible, reconfigurable terminal pin |
US4987319A (en) * | 1988-09-08 | 1991-01-22 | Kawasaki Steel Corporation | Programmable input/output circuit and programmable logic device |
US4982115A (en) * | 1989-02-02 | 1991-01-01 | Rockwell International Corporation | Digital signal direction detection circuit |
US6240496B1 (en) | 1989-11-24 | 2001-05-29 | Hyundai Electronics America | Architecture and configuring method for a computer expansion board |
US5418935A (en) * | 1990-04-30 | 1995-05-23 | Unisys Corporation | Apparatus for preventing double drive occurrences on a common bus by delaying enablement of one driver after indication of disablement to other driver is received |
US5498976A (en) * | 1990-10-26 | 1996-03-12 | Acer Incorporated | Parallel buffer/driver configuration between data sending terminal and data receiving terminal |
US5311081A (en) * | 1992-04-01 | 1994-05-10 | Digital Equipment Corporation | Data bus using open drain drivers and differential receivers together with distributed termination impedances |
US5347177A (en) * | 1993-01-14 | 1994-09-13 | Lipp Robert J | System for interconnecting VLSI circuits with transmission line characteristics |
US5557223A (en) * | 1993-06-08 | 1996-09-17 | National Semiconductor Corporation | CMOS bus and transmission line driver having compensated edge rate control |
WO1994029798A1 (en) * | 1993-06-08 | 1994-12-22 | National Semiconductor Corporation | Programmable cmos bus and transmission line driver |
WO1994029962A1 (en) * | 1993-06-08 | 1994-12-22 | National Semiconductor Corporation | Cmos btl compatible bus and transmission line driver |
US5483184A (en) * | 1993-06-08 | 1996-01-09 | National Semiconductor Corporation | Programmable CMOS bus and transmission line receiver |
US5539341A (en) * | 1993-06-08 | 1996-07-23 | National Semiconductor Corporation | CMOS bus and transmission line driver having programmable edge rate control |
US5543746A (en) * | 1993-06-08 | 1996-08-06 | National Semiconductor Corp. | Programmable CMOS current source having positive temperature coefficient |
US5511170A (en) * | 1993-08-02 | 1996-04-23 | Motorola, Inc. | Digital bus data retention |
GB2341469B (en) * | 1994-11-09 | 2000-04-26 | Adaptec Inc | Serial port for a host adapter integrated circuit using a single terminal |
US5826068A (en) | 1994-11-09 | 1998-10-20 | Adaptec, Inc. | Integrated circuit with a serial port having only one pin |
US5938746A (en) * | 1996-02-29 | 1999-08-17 | Sanyo Electric Co., Ltd. | System for prioritizing slave input register to receive data transmission via bi-directional data line from master |
US5818260A (en) * | 1996-04-24 | 1998-10-06 | National Semiconductor Corporation | Transmission line driver having controllable rise and fall times with variable output low and minimal on/off delay |
US6014036A (en) * | 1997-11-20 | 2000-01-11 | International Business Machines Corporation | Bidirectional data transfer path having increased bandwidth |
US5896337A (en) * | 1998-02-23 | 1999-04-20 | Micron Technology, Inc. | Circuits and methods for multi-level data through a single input/ouput pin |
US6317801B1 (en) * | 1998-07-27 | 2001-11-13 | Intel Corporation | System for post-driving and pre-driving bus agents on a terminated data bus |
US6222413B1 (en) * | 1999-03-16 | 2001-04-24 | International Business Machines Corporation | Receiver assisted net driver circuit |
DE19961727A1 (de) * | 1999-12-21 | 2001-07-05 | Micronas Gmbh | Schaltungsanordnung mit einer Datenübertragungsvorrichtung |
US6725305B1 (en) * | 1999-12-29 | 2004-04-20 | Agere Systems Inc. | Method and apparatus for using a bus as a data storage node |
US6977979B1 (en) | 2000-08-31 | 2005-12-20 | Hewlett-Packard Development Company, L.P. | Enhanced clock forwarding data recovery |
US7840900B1 (en) * | 2009-04-30 | 2010-11-23 | Spansion Llc | Replacing reset pin in buses while guaranteeing system recovery |
Family Cites Families (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3585399A (en) * | 1968-10-28 | 1971-06-15 | Honeywell Inc | A two impedance branch termination network for interconnecting two systems for bidirectional transmission |
US3912948A (en) * | 1971-08-30 | 1975-10-14 | Nat Semiconductor Corp | Mos bootstrap inverter circuit |
US4409671A (en) * | 1978-09-05 | 1983-10-11 | Motorola, Inc. | Data processor having single clock pin |
JPS6037996B2 (ja) * | 1980-02-20 | 1985-08-29 | 沖電気工業株式会社 | バツフア回路 |
US4347600A (en) * | 1980-06-03 | 1982-08-31 | Rockwell International Corporation | Monitored muldem with self test of the monitor |
US4376998A (en) * | 1980-06-03 | 1983-03-15 | Rockwell International Corporation | Muldem with monitor comparing means which accepts different data rates |
JPS5798028A (en) * | 1980-12-10 | 1982-06-18 | Sanyo Electric Co Ltd | Logical circuit |
JPS6347105Y2 (ko) * | 1981-01-13 | 1988-12-06 | ||
JPS5833739A (ja) * | 1981-08-21 | 1983-02-28 | Toshiba Corp | バスライン駆動回路 |
US4414480A (en) * | 1981-12-17 | 1983-11-08 | Storage Technology Partners | CMOS Circuit using transmission line interconnections |
US4567561A (en) * | 1981-12-24 | 1986-01-28 | International Business Machines Corp. | Large scale integration data processor signal transfer mechanism |
US4471243A (en) * | 1982-07-26 | 1984-09-11 | Rca Corporation | Bidirectional interface |
IT1210945B (it) * | 1982-10-22 | 1989-09-29 | Ates Componenti Elettron | Circuito di interfaccia per generatori di segnali di sincronismo a due fasi nonsovrapposte. |
JPS59133624A (ja) * | 1983-01-20 | 1984-08-01 | Sharp Corp | インタ−フエイス方式 |
US4542305A (en) * | 1983-02-22 | 1985-09-17 | Signetics Corporation | Impedance buffer with reduced settling time |
US4558237A (en) * | 1984-03-30 | 1985-12-10 | Honeywell Inc. | Logic families interface circuit and having a CMOS latch for controlling hysteresis |
JPS60252979A (ja) * | 1984-05-30 | 1985-12-13 | Oki Electric Ind Co Ltd | Cmos入出力回路 |
IL75374A (en) * | 1984-06-07 | 1989-02-28 | Motorola Inc | External interface control circuitry for microcomputer systems |
US4625126A (en) * | 1984-06-29 | 1986-11-25 | Zilog, Inc. | Clock generator for providing non-overlapping clock signals |
US4645947A (en) * | 1985-12-17 | 1987-02-24 | Intel Corporation | Clock driver circuit |
-
1987
- 1987-05-01 US US07/044,780 patent/US4774422A/en not_active Expired - Fee Related
-
1988
- 1988-04-26 KR KR1019880701768A patent/KR910007649B1/ko not_active IP Right Cessation
- 1988-04-26 JP JP63503787A patent/JP2532135B2/ja not_active Expired - Fee Related
- 1988-04-26 EP EP88904134A patent/EP0360817B1/en not_active Expired - Lifetime
- 1988-04-26 WO PCT/US1988/001276 patent/WO1988008581A1/en active IP Right Grant
- 1988-04-26 AU AU16845/88A patent/AU599235B2/en not_active Ceased
- 1988-04-26 DE DE88904134T patent/DE3878908T2/de not_active Expired - Fee Related
- 1988-04-29 CA CA000565476A patent/CA1297197C/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US4774422A (en) | 1988-09-27 |
WO1988008581A1 (en) | 1988-11-03 |
DE3878908D1 (de) | 1993-04-08 |
KR910007649B1 (ko) | 1991-09-28 |
AU599235B2 (en) | 1990-07-12 |
DE3878908T2 (de) | 1993-10-14 |
EP0360817B1 (en) | 1993-03-03 |
CA1297197C (en) | 1992-03-10 |
AU1684588A (en) | 1988-12-02 |
JPH01502624A (ja) | 1989-09-07 |
EP0360817A1 (en) | 1990-04-04 |
JP2532135B2 (ja) | 1996-09-11 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
G160 | Decision to publish patent application | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
LAPS | Lapse due to unpaid annual fee |