KR890004808Y1 - Revision signal production circuits of z 80 micro processor - Google Patents

Revision signal production circuits of z 80 micro processor Download PDF

Info

Publication number
KR890004808Y1
KR890004808Y1 KR2019860016730U KR860016730U KR890004808Y1 KR 890004808 Y1 KR890004808 Y1 KR 890004808Y1 KR 2019860016730 U KR2019860016730 U KR 2019860016730U KR 860016730 U KR860016730 U KR 860016730U KR 890004808 Y1 KR890004808 Y1 KR 890004808Y1
Authority
KR
South Korea
Prior art keywords
signal
gate
output
flop
flip
Prior art date
Application number
KR2019860016730U
Other languages
Korean (ko)
Other versions
KR880008441U (en
Inventor
류근배
Original Assignee
삼성전자 주식회사
한형수
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 삼성전자 주식회사, 한형수 filed Critical 삼성전자 주식회사
Priority to KR2019860016730U priority Critical patent/KR890004808Y1/en
Publication of KR880008441U publication Critical patent/KR880008441U/en
Application granted granted Critical
Publication of KR890004808Y1 publication Critical patent/KR890004808Y1/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/0721—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment within a central processing unit [CPU]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Executing Machine-Instructions (AREA)

Abstract

내용 없음.No content.

Description

Z 80 마이크로 프로세서의 보정신호 발생회로Calibration signal generation circuit of Z 80 microprocessor

제1도는 본 고안의 회로도.1 is a circuit diagram of the present invention.

제2도는 본 고안의 회로도의 각부 파형도.2 is a waveform diagram of each part of the circuit diagram of the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

D0∼D7: 데이타 신호: 리드신호(READ)D 0 to D 7 : data signal : Lead signal (READ)

: 보정신호: 제어신호(OP코드 패취싸이클 신호) : Correction signal : Control signal (OP code patch cycle signal)

A1∼A5: 앤드게이트 I1∼I3: 인버터A 1 to A 5 : AND gate I 1 to I 3 : inverter

FF : 플립플롭 OR1∼OR2: 오아게이트FF: Flip-flop OR 1- OR 2 : Oagate

본 고안은 Z 80 마이크로 프로세서의 보정신호 발생회로에 관한 것이다.The present invention relates to a correction signal generation circuit of the Z 80 microprocessor.

Z 80 마이크로 프로세서(CPU)는 그 내부 구조나 명령어가 인텔사의 8080과 호환성 있게 만들어져 있으며 8080보다 더 많은 기능을 갖게 하게 위하여 8080에서는 사용하지 않는 12개분의 오피 코드(OP CODE)를 더 사용하여 명령어를 추가하고 있다.The Z 80 microprocessor (CPU) uses 12 more OP CODEs not used by the 8080 to make its internal structure or instructions compatible with the Intel 8080 and to provide more functionality than the 8080. Is adding.

그러나 Z 80 의 27번째핀에서 발생되는 OP 코드 패취싸이클(: 이하 제어신호라 칭함)가 각 명령어의 첫번째 머신싸이클에서 「L레벨」신호로 출력되게 되어 있지만 다른 오피 코드의 명령어(CB, DD, ED, FD)로 시작되는 명령어는 두번째 머신 싸이클에서도 제어신호()가 출력되므로 명령어 단위로 카운팅을 하고자 할때에는 불편한 것이었다.However, the OP code patch cycle that occurs on pin 27 of Z 80 ( (Low control signal) is output as "L level" signal in the first machine cycle of each instruction, but instructions starting with instructions of other op codes (CB, DD, ED, FD) are also control signals in the second machine cycle. ( ) Would be inconvenient when counting by command.

따라서 하드웨어적으로 제어신호()의 펄스를 이용하여 여러가지 개발용 장비를 설계하고자 할때에는 첫번째 머신 싸이클에서만 제어신호()가 발생하게 할 필요가 있다.Therefore, the control signal ( When designing various equipment for development using the pulse of), the control signal ( ) Needs to occur.

본 고안은 이와 같은 제어신호를 하드웨어적으로 보정시켜 다른 오피 코드의 명령어 수행중에도 첫번째 머신싸이클시 보정된 제어신호가 출력되게 하여 여러가지 개발용 장비에 널리 사용하기 쉽게함을 목적으로 하는 것으로, 각각의 데이타 신호가 앤드게이트, 인버터, 오아게이트, 노아게이트를 통하여 리드신호(클럭신호로써 인사되는) 플립플롭의 입력단자에 인가되게 구성시킨 후 플립플롭 출력단자에 연결된 오아게이트의 타측으로 제어신호가 인가되게 구성시킨 것이다.The present invention aims to make the control signal corrected by hardware so that the corrected control signal is output during the first machine cycle even during the execution of other op codes. The data signal is configured to be applied to an input terminal of a read signal (greeted as a clock signal) through a AND gate, an inverter, an ora gate, and a no-gate, and then a control signal is applied to the other side of the or gate connected to the flip-flop output terminal. It is configured.

이를 첨부 도면에 의하여 상세히 설명하면 다음과 같다.This will be described in detail with reference to the accompanying drawings.

제1도는 본 고안의 회로도로서 OP코드 명령어 수행시 인가되는 데이타신호(D7) (D6) (D3) (D0)는 앤드게이트 (A1)를 통하여 출력되게 구성하며 데이타 신호(D5) (D4)는 오아게이트(OR1) 및 인버터(I1)를 통하여 각각 앤드게이트(A2) (A3)에 인가되게 구성시킨 후 데이타신호(D1)(D2)가 인버터(I2) (I3)를 통하여 앤드게이트 (A4) (A5)로 출력되게 구성시킨다.1 is a circuit diagram of the present invention, the data signal (D 7 ) (D 6 ) (D 3 ) (D 0 ) applied when an OP code instruction is executed is configured to be output through an AND gate (A 1 ), and the data signal (D) 5 ) (D 4 ) is configured to be applied to the AND gate (A 2 ) (A 3 ) through the oragate (OR 1 ) and inverter (I 1 ), respectively, and then the data signal (D 1 ) (D 2 ) is applied to the inverter. (I 2 ) is configured to be output to the AND gate (A 4 ) (A 5 ) through (I 3 ).

그리고 앤드게이트(A4) (A5) 의 출력이 노아게이트(NO1) (NO2)를 통하여 리드신호 ()가 클럭 신호로써 인가되는 플립플롭(FF)의 입력단자(D)에 인가되게 구성시킨 후 출력단자(Q)에 오아게이트 (OR2)를 연설 구성시키고 제어신호(M1)와 같이 출력되게 구성시킨 것이다.The output of the AND gate A 4 and A 5 is connected to the read signal through the NOA gate NO 1 and NO 2 . ) Is configured to be applied to the input terminal (D) of the flip-flop (FF) to be applied as a clock signal, and then the oragate (OR 2 ) is configured to be output to the output terminal (Q) and output as the control signal (M 1 ). It is made up.

이와 같이 구성된 본 고안에서 Z 80 마이크로 프로세서(CPU)는 인텔사의 8080마이크로 프로세서 OP코드를 꼭 같이 가질 뿐만 아니라 전술한 바와 같이 12개의 추가 OP코드를 갖고 있으며, 그 중에 4가지의 OP코드는 CB, DD, ED, FD 의 2바이트 OP코드로써 각각의 데이타 신호는 다음표와 같이 나타나게 된다.In this design, the Z 80 microprocessor (CPU) not only has the 8080 microprocessor OP code of Intel Corporation, but also has 12 additional OP codes as described above, and four of the OP codes are CB, Each data signal is a two-byte OP code of DD, ED, and FD as shown in the following table.

따라서 4개의 OP 코드에서는 데이타 신호 (D7) (D6) (D3) (D0)는 모두 「H레벨」신호로써 출력되므로 앤드게이트(A1)를 통하여「H레벨」신호가 출력하게 되고 데이타 신호 (D5)(D4)는 각각 인가되는 OP코드에 따라 상이함으로 오아게이트(OR1)와 인버터(I1) 를 통하여 앤드게이트(A2)(A3)로 출력되게 하므로써 다른 데이타 신호 (D7) (D6) (D3) (D0)에 의하여 OP코드로써 식별하게 된다.Therefore, in the four OP codes, the data signals D 7 , D 6 , D 3 , and D 0 are all output as the "H level" signal, so that the "H level" signal is output through the AND gate A 1 . And the data signals D 5 and D 4 are different according to the applied OP codes, respectively, so that the data signals D 5 and D 4 are outputted to the AND gate A 2 and A 3 through the oragate OR 1 and the inverter I 1 . The data signal D 7 (D 6 ) (D 3 ) (D 0 ) identifies the OP code.

그리고 데이타 신호(D2) (D1)는 서로 반대신호이므로 인버터 (I2) (I3)및 앤드게이트(A4) (A5)를 통하여 출력되게 하여 노아게이트(NO1) (NO2)를 제어하게 된다.And the data signal (D 2) (D 1) because it is opposite to each other signal inverter (I 2) (I 3) and the AND gate (A 4) (A 5) to be outputted through the NOR gate (NO 1) (NO 2 Will be controlled.

즉, 평상시 플립플롭(FF)의 출력단자(Q)는 「L레벨」의 신호가 노아게티트(NOR2)를 통하여 출력되므로 다른 명령어와 동일하게 수행되고 특정된 4개의 OP코드(CB, DD, ED, FD)중 어느 하나가 데이타 버스에 인가될때는 플립플롭(FF)의 출력단자(Q)가 「L레벨」에 있으므로 보정신호 ()는 오아게이트(OR2)를 통하여 보정신호 ()로 그대로 통과하여 제2도와 같이 처음 보정신호()의 신호는 보정신호 ()와 같이 된다.That is, since the output terminal Q of the flip-flop FF is normally outputted through the no-gate (NOR 2 ) signal, four OP codes CB and DD are executed in the same way as other instructions. Is applied to the data bus, the output terminal Q of the flip-flop FF is at " L level " ) Is the correction signal (O 2 through OR 2 ) ) And pass the first correction signal as shown in FIG. ) Signal is corrected signal ( )

그러나 리드신호()에 의하여 플립플롭(FF)의 입력단자(D)에 인가된 「H레벨」신호가 출력단자(Q)에 전달되어 각각의 OP코드(CB, DD, ED, FD)와 연결되는 2번째 바이트의 OP 코드 페취시에는 보정신호 ()의 「L레벨」신호와 플립플롭(FF)의 출력신호(Q)의 「H레벨」이 오아게이트(OR2)를 통하여 「H 레벨」로 출력되므로 2바이트의 OP코드 명령어 수행시 연속되는 두개의 보정신호 ()를 보정하여 하나의 보정신호()만 출력하게 되는 것이다.However, the lead signal ( Is transmitted to the output terminal Q by the " H level " signal applied to the input terminal D of the flip-flop FF, and is connected to the respective OP codes CB, DD, ED and FD. When the OP code is fetched, the correction signal ( ) "L level" is "H level" of the output signal (Q) of the signal and a flip-flop (FF) Iowa gate (since the output "H level" through the OR 2) successive in performing a 2-byte OP code instructions of Two correction signals ( ) By correcting one correction signal ( ) Will be printed.

이상에서와 같이 본 고안은 각각의 논리 소자로써 플립플롭의 출력이 제어되게 구성하여 특정된 OP코드의 명령이 수행될때의 한번의 보정신호()만을 출력시ㅌ켜 OP코드 페취싸이클 신호로써 명령의 단위로 카운팅을 행할 수가 있어 여러가지 개발용 장비에 널리 유용되게 사용할 수 있는 이점이 있는 것이다.As described above, the present invention is configured such that the output of the flip-flop is controlled by each logic element so that one correction signal when a command of a specific OP code is performed ( ) Can be counted as a unit of command as an OP code fetch cycle signal, which has the advantage that it can be widely used for various development equipment.

Claims (1)

각각의 테이타 신호(D0∼D7) 가 앤드게이트(A1∼A5), 인버터( I1∼I3), 오아게이트 (OR1), 노아게이트(NO1) (NO2) 를 통하여 리드신호 ()가 클럭신호로써 인가되는 플립플롭(FF)의 입력단자(D)에 인가되게 구성시킨 후 플립플롭(FF)의 출력단자(Q)에 연결된 오아게이트(OR2)의 타측으로 제어신호()가 인가되게 구성시킨 Z 80 마이크로 프로세서의 보정신호 발생회로.Each of the data signals D 0 to D 7 passes through an AND gate A 1 to A 5 , an inverter I 1 to I 3 , an oragate OR 1 , and a noa gate NO 1 (NO 2 ). Lead signal ) Is applied to the input terminal D of the flip-flop FF, which is applied as a clock signal, and then to the other side of the oragate OR 2 connected to the output terminal Q of the flip-flop FF. Correction signal generating circuit of the Z 80 microprocessor configured to be applied.
KR2019860016730U 1986-10-31 1986-10-31 Revision signal production circuits of z 80 micro processor KR890004808Y1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR2019860016730U KR890004808Y1 (en) 1986-10-31 1986-10-31 Revision signal production circuits of z 80 micro processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR2019860016730U KR890004808Y1 (en) 1986-10-31 1986-10-31 Revision signal production circuits of z 80 micro processor

Publications (2)

Publication Number Publication Date
KR880008441U KR880008441U (en) 1988-06-29
KR890004808Y1 true KR890004808Y1 (en) 1989-07-20

Family

ID=19256662

Family Applications (1)

Application Number Title Priority Date Filing Date
KR2019860016730U KR890004808Y1 (en) 1986-10-31 1986-10-31 Revision signal production circuits of z 80 micro processor

Country Status (1)

Country Link
KR (1) KR890004808Y1 (en)

Also Published As

Publication number Publication date
KR880008441U (en) 1988-06-29

Similar Documents

Publication Publication Date Title
US4839797A (en) Microprocessor compatible with any software represented by different types of instruction formats
US4618849A (en) Gray code counter
KR890004808Y1 (en) Revision signal production circuits of z 80 micro processor
JPS6046749B2 (en) Interrupt circuit to computer
JPS6234355Y2 (en)
KR900006703Y1 (en) Circuit for the delay of m1 signal in z-80
KR100446150B1 (en) Apparatus for identifying daughter board in digital exchanger
SU1536379A2 (en) Microprogram control device
JPH04306013A (en) Latch circuit device
KR950001439Y1 (en) R-s flip flop
JPH0619700B2 (en) Arithmetic unit
KR930004310Y1 (en) Odd number frequency division circuit
KR890003752Y1 (en) Reset circuit
KR930002025Y1 (en) Clock-switching circuit
JPS63250743A (en) Test mode setting system
KR890003687B1 (en) Control circuit of dual port's memory
KR930004767Y1 (en) Analog and digital curcuit capable of state conformated
JPS54130842A (en) Method address generator
KR890004811Y1 (en) Micro processor & interface circuits of bus
KR860002287Y1 (en) Circuit for speed regulation of motor
JP2568744Y2 (en) Switching circuit for bidirectional input / output port of one-chip microcomputer
KR900003664B1 (en) A modem control circuit
JPS63111730A (en) Code error detection circuit
JPH01123333A (en) Computer
KR920013179A (en) Data Transceiver Circuit of Fieldbus Interface Board

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
REGI Registration of establishment
FPAY Annual fee payment

Payment date: 19950701

Year of fee payment: 7

LAPS Lapse due to unpaid annual fee