KR880700452A - 실리콘에의 보론 도우핑 방법 - Google Patents
실리콘에의 보론 도우핑 방법Info
- Publication number
- KR880700452A KR880700452A KR1019860700659A KR860700659A KR880700452A KR 880700452 A KR880700452 A KR 880700452A KR 1019860700659 A KR1019860700659 A KR 1019860700659A KR 860700659 A KR860700659 A KR 860700659A KR 880700452 A KR880700452 A KR 880700452A
- Authority
- KR
- South Korea
- Prior art keywords
- silicon
- doping method
- boron doping
- boron
- doping
- Prior art date
Links
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 title 1
- 229910052796 boron Inorganic materials 0.000 title 1
- 229910052710 silicon Inorganic materials 0.000 title 1
- 239000010703 silicon Substances 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/92—Capacitors having potential barriers
- H01L29/94—Metal-insulator-semiconductors, e.g. MOS
- H01L29/945—Trench capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
- H01L21/2251—Diffusion into or out of group IV semiconductors
- H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
- H01L21/2255—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer comprising oxides only, e.g. P2O5, PSG, H3BO3, doped oxides
- H01L21/2256—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer comprising oxides only, e.g. P2O5, PSG, H3BO3, doped oxides through the applied layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76237—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/914—Doping
- Y10S438/923—Diffusion through a layer
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US06/694,806 US4604150A (en) | 1985-01-25 | 1985-01-25 | Controlled boron doping of silicon |
PCT/US1985/002501 WO1986004454A1 (en) | 1985-01-25 | 1985-12-16 | Controlled boron doping of silicon |
Publications (1)
Publication Number | Publication Date |
---|---|
KR880700452A true KR880700452A (ko) | 1988-03-15 |
Family
ID=24790354
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019860700659A KR940008018B1 (ko) | 1985-01-25 | 1985-12-16 | 직접 회로 제조 방법 |
KR1019860700659A KR880700452A (ko) | 1985-01-25 | 1986-09-24 | 실리콘에의 보론 도우핑 방법 |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019860700659A KR940008018B1 (ko) | 1985-01-25 | 1985-12-16 | 직접 회로 제조 방법 |
Country Status (8)
Country | Link |
---|---|
US (1) | US4604150A (ko) |
EP (1) | EP0210190B1 (ko) |
JP (1) | JPS62501530A (ko) |
KR (2) | KR940008018B1 (ko) |
CA (1) | CA1286573C (ko) |
DE (1) | DE3583612D1 (ko) |
ES (1) | ES8704553A1 (ko) |
WO (1) | WO1986004454A1 (ko) |
Families Citing this family (40)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61202426A (ja) * | 1985-03-05 | 1986-09-08 | Matsushita Electric Ind Co Ltd | 半導体装置の製造方法 |
US4653177A (en) * | 1985-07-25 | 1987-03-31 | At&T Bell Laboratories | Method of making and selectively doping isolation trenches utilized in CMOS devices |
US4679300A (en) * | 1985-10-07 | 1987-07-14 | Thomson Components-Mostek Corp. | Method of making a trench capacitor and dram memory cell |
KR870004517A (ko) * | 1985-10-07 | 1987-05-11 | 아르레뜨 다낭제 | 실리콘 집적회로 및 cmos집적회로 제조시 중간 절연방법 |
USRE35036E (en) * | 1986-06-13 | 1995-09-12 | Matsushita Electric Industrial Co., Ltd. | Method of making symmetrically controlled implanted regions using rotational angle of the substrate |
US4771012A (en) * | 1986-06-13 | 1988-09-13 | Matsushita Electric Industrial Co., Ltd. | Method of making symmetrically controlled implanted regions using rotational angle of the substrate |
JPH01287956A (ja) * | 1987-07-10 | 1989-11-20 | Toshiba Corp | 半導体記憶装置およびその製造方法 |
US5851871A (en) * | 1987-12-23 | 1998-12-22 | Sgs-Thomson Microelectronics, S.R.L. | Process for manufacturing integrated capacitors in MOS technology |
JP2706469B2 (ja) * | 1988-06-01 | 1998-01-28 | 松下電器産業株式会社 | 半導体装置の製造方法 |
US4963502A (en) * | 1988-08-25 | 1990-10-16 | Texas Instruments, Incorporated | Method of making oxide-isolated source/drain transistor |
IT1225625B (it) * | 1988-11-03 | 1990-11-22 | Sgs Thomson Microelectronics | Procedimento per la realizzazione di strutture di isolamento incassate nel substrato di silicio per dispositivi cmos ed nmos. |
US5084418A (en) * | 1988-12-27 | 1992-01-28 | Texas Instruments Incorporated | Method of making an array device with buried interconnects |
US5143859A (en) * | 1989-01-18 | 1992-09-01 | Mitsubishi Denki Kabushiki Kaisha | Method of manufacturing a static induction type switching device |
US5264381A (en) * | 1989-01-18 | 1993-11-23 | Mitsubishi Denki Kabushiki Kaisha | Method of manufacturing a static induction type switching device |
US5108938A (en) * | 1989-03-21 | 1992-04-28 | Grumman Aerospace Corporation | Method of making a trench gate complimentary metal oxide semiconductor transistor |
WO1990011616A1 (en) * | 1989-03-21 | 1990-10-04 | Grumman Aerospace Corporation | Trench gate complimentary metal oxide semiconductor transistor |
EP0445471A3 (en) * | 1990-03-06 | 1994-10-26 | Digital Equipment Corp | Method of forming isolation trenches in a semiconductor substrate |
US5242858A (en) * | 1990-09-07 | 1993-09-07 | Canon Kabushiki Kaisha | Process for preparing semiconductor device by use of a flattening agent and diffusion |
US5273934A (en) * | 1991-06-19 | 1993-12-28 | Siemens Aktiengesellschaft | Method for producing a doped region in a substrate |
EP0631305B1 (de) * | 1993-06-23 | 1998-04-15 | Siemens Aktiengesellschaft | Verfahren zur Herstellung eines Isolationsgrabens in einem Substrat für Smart-Power-Technologien |
EP0631306B1 (de) * | 1993-06-23 | 2000-04-26 | Siemens Aktiengesellschaft | Verfahren zur Herstellung von einem Isolationsgraben in einem Substrat für Smart-Power-Technologien |
US6730549B1 (en) | 1993-06-25 | 2004-05-04 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for its preparation |
JPH0766424A (ja) * | 1993-08-20 | 1995-03-10 | Semiconductor Energy Lab Co Ltd | 半導体装置およびその作製方法 |
JP3396553B2 (ja) * | 1994-02-04 | 2003-04-14 | 三菱電機株式会社 | 半導体装置の製造方法及び半導体装置 |
US6706572B1 (en) | 1994-08-31 | 2004-03-16 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing a thin film transistor using a high pressure oxidation step |
US5451809A (en) * | 1994-09-07 | 1995-09-19 | Kabushiki Kaisha Toshiba | Smooth surface doped silicon film formation |
JP3306258B2 (ja) * | 1995-03-27 | 2002-07-24 | 三洋電機株式会社 | 半導体装置の製造方法 |
US5888876A (en) * | 1996-04-09 | 1999-03-30 | Kabushiki Kaisha Toshiba | Deep trench filling method using silicon film deposition and silicon migration |
TW304293B (en) * | 1996-11-18 | 1997-05-01 | United Microelectronics Corp | Manufacturing method for shallow trench isolation |
US6326293B1 (en) * | 1997-12-19 | 2001-12-04 | Texas Instruments Incorporated | Formation of recessed polysilicon plugs using chemical-mechanical-polishing (CMP) and selective oxidation |
US6107153A (en) * | 1998-01-26 | 2000-08-22 | Texas Instruments -Acer Incorporated | Method of forming a trench capacitor for a DRAM cell |
TW379417B (en) * | 1998-06-04 | 2000-01-11 | United Semiconductor Corp | Buried bitline structure and the manufacture method |
DE19939589B4 (de) * | 1999-08-20 | 2004-08-12 | Infineon Technologies Ag | Verfahren zur Herstellung eines Grabens mit vergrabener Platte |
US6891209B2 (en) * | 2001-08-13 | 2005-05-10 | Amberwave Systems Corporation | Dynamic random access memory trench capacitors |
EP1868239B1 (en) * | 2006-06-12 | 2020-04-22 | ams AG | Method of manufacturing trenches in a semiconductor body |
EP2311072B1 (en) * | 2008-07-06 | 2013-09-04 | Imec | Method for doping semiconductor structures |
KR101095802B1 (ko) * | 2010-01-07 | 2011-12-21 | 주식회사 하이닉스반도체 | 반도체 소자 및 그의 제조 방법 |
US8940388B2 (en) | 2011-03-02 | 2015-01-27 | Micron Technology, Inc. | Insulative elements |
CN102254801B (zh) * | 2011-08-06 | 2013-06-19 | 深圳市稳先微电子有限公司 | 一种精确控制半导体器件掺杂区掺杂浓度的方法 |
CN115172518A (zh) * | 2022-07-08 | 2022-10-11 | 酒泉正泰新能源科技有限公司 | 一种太阳能电池的多次氧化扩散方法、制备方法 |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3928095A (en) * | 1972-11-08 | 1975-12-23 | Suwa Seikosha Kk | Semiconductor device and process for manufacturing same |
JPS501986A (ko) * | 1973-05-09 | 1975-01-10 | ||
NL7604445A (nl) * | 1976-04-27 | 1977-10-31 | Philips Nv | Werkwijze ter vervaardiging van een halfgelei- derinrichting, en inrichting vervaardigd door toepassing van de werkwijze. |
NL7710635A (nl) * | 1977-09-29 | 1979-04-02 | Philips Nv | Werkwijze voor het vervaardigen van een halfgeleiderinrichting. |
US4353086A (en) * | 1980-05-07 | 1982-10-05 | Bell Telephone Laboratories, Incorporated | Silicon integrated circuits |
US4397075A (en) * | 1980-07-03 | 1983-08-09 | International Business Machines Corporation | FET Memory cell structure and process |
DE3129558A1 (de) * | 1980-07-28 | 1982-03-18 | Tokyo Shibaura Denki K.K., Kawasaki, Kanagawa | Verfahren zur herstellung einer integrierten halbleiterschaltung |
US4356211A (en) * | 1980-12-19 | 1982-10-26 | International Business Machines Corporation | Forming air-dielectric isolation regions in a monocrystalline silicon substrate by differential oxidation of polysilicon |
US4407058A (en) * | 1981-05-22 | 1983-10-04 | International Business Machines Corporation | Method of making dense vertical FET's |
US4502202A (en) * | 1983-06-17 | 1985-03-05 | Texas Instruments Incorporated | Method for fabricating overlaid device in stacked CMOS |
US4502894A (en) * | 1983-08-12 | 1985-03-05 | Fairchild Camera & Instrument Corporation | Method of fabricating polycrystalline silicon resistors in integrated circuit structures using outdiffusion |
US4569850A (en) * | 1983-11-23 | 1986-02-11 | Auburn Research Foundation | Method for thermally blasting outer coverings from food products |
US4569701A (en) * | 1984-04-05 | 1986-02-11 | At&T Bell Laboratories | Technique for doping from a polysilicon transfer layer |
US4549914A (en) * | 1984-04-09 | 1985-10-29 | At&T Bell Laboratories | Integrated circuit contact technique |
US4534824A (en) * | 1984-04-16 | 1985-08-13 | Advanced Micro Devices, Inc. | Process for forming isolation slots having immunity to surface inversion |
-
1985
- 1985-01-25 US US06/694,806 patent/US4604150A/en not_active Expired - Lifetime
- 1985-12-16 KR KR1019860700659A patent/KR940008018B1/ko active
- 1985-12-16 WO PCT/US1985/002501 patent/WO1986004454A1/en active IP Right Grant
- 1985-12-16 DE DE8686900515T patent/DE3583612D1/de not_active Expired - Fee Related
- 1985-12-16 JP JP61500503A patent/JPS62501530A/ja active Pending
- 1985-12-16 EP EP86900515A patent/EP0210190B1/en not_active Expired - Lifetime
-
1986
- 1986-01-21 CA CA000500041A patent/CA1286573C/en not_active Expired - Fee Related
- 1986-01-24 ES ES551229A patent/ES8704553A1/es not_active Expired
- 1986-09-24 KR KR1019860700659A patent/KR880700452A/ko not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
EP0210190B1 (en) | 1991-07-24 |
ES8704553A1 (es) | 1987-04-16 |
KR940008018B1 (ko) | 1994-08-31 |
US4604150A (en) | 1986-08-05 |
JPS62501530A (ja) | 1987-06-18 |
DE3583612D1 (de) | 1991-08-29 |
CA1286573C (en) | 1991-07-23 |
ES551229A0 (es) | 1987-04-16 |
WO1986004454A1 (en) | 1986-07-31 |
EP0210190A1 (en) | 1987-02-04 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
E902 | Notification of reason for refusal | ||
G160 | Decision to publish patent application | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 20010731 Year of fee payment: 8 |
|
LAPS | Lapse due to unpaid annual fee |